Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-08-26
2004-01-06
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06675359
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to use of high-level integrated circuit description languages. More particularly, the present invention relates to analysis of high-level integrated circuit description language to identify code sequences defining integrated circuit implementations of state machines.
BACKGROUND OF THE INVENTION
High-level integrated circuit (IC) description languages such as VHDL and Verilog® (M are commonly used to design circuits. One embodiment of VHDL is described in greater detail in “IEEE Standard VHDL Language Reference Manual,” ANSI Std. 1076-1993, published Jun. 6, 1994. One embodiment of Verilog® is described in greater detail in “IEEE Standard Hardware Description Language Based on the Verilog® Hardware Description Language,” IEEE Standard 1364-1995, published Oct. 14, 1996. These high-level IC description languages allow a circuit designer to design and simulate circuits by using high-level code to describe the structure and/or behavior of the circuit being designed.
The high-level IC description language code is used to produce a netlist that describes an interconnection of circuit components to provide desired functionality. The netlist can then be used to develop the layout and ultimately fabricate an IC having the functionality of the designed circuit. The netlist can also be used for verification purposes.
Over time, many complex circuits have been designed using high-level IC description languages. The complexity of the code describing the circuits increases with the complexity of the circuit described, which in turn increases the cost of modifications to customize the circuit for new environments especially if the code is poorly documented and/or the original circuit designer is not available.
One component of a circuit design that is often modified to adapt the circuit design to a new environment is the state machine. A state machine is often used for control purposes, which is dependent on the environment in which the circuit design must operate. Therefore, in order to modify the circuit design to operate in a new environment, the state machine is often modified accordingly.
What is needed is a tool for recognizing and extracting state machines from high-level IC description language code.
SUMMARY OF THE INVENTION
A method and apparatus for identifying a integrated circuit (IC) implementation of a state machine in high-level IC description language code is described. One or more transition processes within the high-level IC description language code are identified. A state machine summary is built based at least in part on the one or more transition processes identified.
In one embodiment, one or more clocked processes and one or more output processes are also identified. A state machine summary is built based at least in part on the one or more transition processes, the one or more clocked processes and the one or more output processes. In one embodiment, the state machine summary is a textual description of the state machine. Alternatively, the state machine summary is a graphical representation of the state machine.
REFERENCES:
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patent: 6182268 (2001-01-01), McElvain
Hoskote et al “Automated Verification of Temporal Properties Specified as State Machine in VHDL,” IEEE, 1995, pp. 100-105.*
Kam et al “Comparing Layouts with HDL Models: A Formal Verification Technique,” IEEE, Apr. 4, 1995.*
Cheng et al “Compiling Verilog Into Timed Finite State Machines,” IEEE, 1995, pp. 32-39.*
Wu et al “A Synthesis Method for Mixed Synchronous/Asynchronous Behavior,” IEEE, 1994, pp. 277-281.*
“IEEE Standard VHDL Language Reference Manual,” ANSI Std. 1076-1993, Published Jun. 6, 1994.
“IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language,” IEEE Standard 1364-1995, Published Oct. 14, 1996.
Dane Mark W.P.
Gilford Michael E.J.
Reynolds Michael J.
Tredinnick Jacob L.
Walker Gordon N.
Klarquist & Sparkman, LLP
Siek Vuthe
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