Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-17
2001-02-20
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S694000, C118S715000, C118S725000, C118S730000, C427S248100
Reexamination Certificate
active
06191035
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly to a method and apparatus for preventing undesirable deposits of tungsten (W) on the backside of semiconductor wafers.
(2) Description of the Prior Art
During the multitude of processes in building a semiconductor device on the polished frontside of a wafer, the backside (unpolished side) of the wafer can be inadvertently exposed to the same processes as directed upon the frontside. In many instances, such exposure is inconsequential since the following process operations are tolerant or remedial of such exposure. However, in other process steps, the result of such exposure is detrimental and can prove troublesome in those subsequent processes and can ultimately limit the yield of good semiconductor devices from the wafer.
Well known in the semiconductor industry, is the problem of chemical vapor deposition (CVD) materials loosely adhering to the unprotected backside of a wafer. Such is the case when depositing tungsten (W). The mechanism for the problem is where tungsten flouride (WF
6
) reacts with hydrogen (H
2
) forming tungsten (W) on the frontside of the wafer and (HF) which inadvertently flows to regions at the backside of a wafer. There, additional WF
6
reacts with Silicon (Si) to form a nucleation layer of tungsten (W) as well as silicon flouride (SiF
4
). Continued backside reaction of tungsten flouride (WF
6
) with hydrogen (H
2
) deposits tungsten (W) and produces additional HF. The HF then reacts with the native oxide which causes additional polysilicon to be exposed to tungsten flouride (WF
6
).
Some of these partially coated backside materials become detached in subsequent processes and form particulates which can cause fatal defects in the evolving semiconductor devices. Also excessive uneven buildup of adhering deposited material on the backside of the wafer can deplanarize the backside, rendering the backside ineffective as a planar datum to assure accurate processing of the frontside, such as maintaining a consistent depth of focus during a photolithographic exposure operation. With respect to the current invention the problem is that a thin film of tungsten is deposited regionally on a backside layer of polysilicon which prevents subsequent stripping of the polysilicon results in a nonplanar wafer backside.
To avoid these kinds of problems, firstly, the unprotected backside of the wafer could be subsequently stripped of its undesirable deposited materials, resulting in an additional manufacturing step which adds to the cost and exposes the wafer to additional yield detracting handling. Or, secondly, the wafer backside could be protected from the deposition processes.
In one solution of the first kind, U.S. Pat. No. 5,384,008 (Ashok Sinha et al.) discloses a process and apparatus which utilizes a necessary subsequent etching process step to remedy a backside deposition problem by use of a reduced size wafer pedestal. However, the deposited material removal is limited to a generally annular area at the periphery of the backside of the wafer. It does not address the problem of deposits near the center of the backside of the wafer which is the problem necessitating the present invention, Furthermore, it does not address the general problem of being an added costly manufacturing step for depositions not requiring an immediate subsequent etching step. Yet, this procedure does make maximum use of semiconductor “real-estate” at the periphery of the frontside of the wafer in that no protective device shields any part of the frontside of the wafer.
Solutions of the second kind are varied to include shadow rings which interfere with making maximum use of wafer frontside “real estate”; wafer periphery seal clamps which in themselves can be a source of particulate generation; and control of chamber gas flow in a relatively non contacting gap near the periphery of the wafer; all of which require additional equipment hardware associated with the wafer chucking heater platen.
U.S. Pat. No. 5,679,405 (Thomas et al) discloses a method whereby a heated inert gas is introduced beneath the wafer and vents at the periphery preventing process gases from contacting the backside of the wafer. The backside pressure is adjusted to compensate for the process pressure which is typically about 10 torr, the difference in pressure being between 1-5 torr, thus maintaining the chucking action.
U.S. Pat. No. 5,620,525 (van de Ven et al.) discloses an apparatus which supplies an inert gas at a greater pressure than the process chamber pressure to an annulus formed by a guard ring and the platen at the periphery of the wafer, thus not interfering with the chucking action, but requiring a guard ring design that will not interfere with the deposition process on the wafer frontside.
U.S. Pat. No. 5,769,951 (van de Ven et al.) further discloses similar apparatus but with shadowing device features.
U.S. Pat. No. 5,505,779 (Mizuno et al.) uses a similar method but establishes an optimum ratio of gap size to inert gas flow rate to control the location of the peripheral portion of the deposited thin film.
The mechanisms producing the undesirable deposits of contamination material are varied and can be due to some ancillary portion of the overall deposition process. All of the above prior art deal with either the remedy for or the prevention of deposition on the wafer backside occasioned during the main phase of the deposition process, but do not address the problem of inadvertent backside deposition during the CVD chamber purge phase in which the residual deposition gases are removed from the chamber after deposition and during the equalization phase in which the pressure across the front and back sides of the wafer is equalized.
SUMMARY OF THE INVENTION
A principal object of the present invention is to prevent the deposition of tungsten (W) or other refractory materials on the backside of a wafer during the purge and equalization phases following the chemical vapor deposition of tungsten (W) or other refractory materials upon the frontside of the wafer.
Another object of the present invention is to provide a new recipe for operation and control of the gases and the pressures in a CVD apparatus to preclude the undesirable deposition of refractory materials on the backside to the wafer.
An additional object of the present invention is to avoid making modifications to the existing equipment either within the chamber, primarily to the heater platen and wafer chucking means or to the piping by utilizing the new recipe for operation and control of the gases and the pressures therein.
Yet another object of the present invention is to improve purge efficiency after the deposition phase by decreasing chamber pressure to reduce the residual gas concentration.
In accordance with the objects of this invention a new method (recipe) for the application of chamber and wafer backside gases at optimum pressures is employed.
A wafer is vacuum chucked on a planar heater platen in a chemical vapor deposition chamber exposing the wafer frontside to a shower of chemical vapors for the purpose of depositing tungsten on the entire frontside of the wafer. The vacuum chucking device operates to generally provide a seal between the chamber deposition gases and the wafer backside vacuum as well as providing stability to meet wafer orientation requirements. Additionally, a specified flow of argon gas is directed to the backside of the wafer during the deposition and purge phases. A specified sequence and range of gas pressures is applied to the front and back sides of the wafer. The inventive step in this approach is found in the modification of the pressures and flow of the inert gas during the purge and equalization phases.
REFERENCES:
patent: 5230741 (1993-07-01), Ven et al.
patent: 5374594 (1994-12-01), Ven et al.
patent: 5384008 (1995-01-01), Sinha et al.
patent: 5505779 (1996-04-01), Mizuno et al.
patent: 5620525 (1997-04-01), van de Ven et al.
patent: 5679405 (1997-10-01)
Cheng Kuo-Hsien
Fan Chen-Mei
Ackerman Stephen B.
Bowers Charles
Lee Hsien-Ming
Saile George O.
Taiwan Semiconductor Manufacturing Company
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