Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-29
2004-05-11
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S382000, C257S377000, C257S385000, C438S244000, C438S387000
Reexamination Certificate
active
06734486
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof, and particularly to a semiconductor device having a plurality of circuit parts with different structures, like a memory cell part and logic circuitry, mixed on one substrate, and a manufacturing method thereof.
2. Description of the Background Art
With the improvements toward higher integration and larger capacities in semiconductor devices, particularly in dynamic RAMs (DRAMs), three-dimensionalization of the memory cells have been studied after the 4M (Mega) DRAM generation for the purposes of maintaining soft-error resistance and securing capacitances of the capacitors. The structures for three-dimensional memory cells have been selected as the DRAM generation advances, and they are now being converged into stacked capacitor cells and trench capacitor cells.
In contrast with the trench capacitor cells in which a trench is formed in a silicon substrate to ensure the capacitances of capacitors with the depth, capacitors are stacked on a silicon substrate in the stacked capacitor cells to ensure the capacitances of the capacitors with the height. Typical stacked capacitor cells include the thick-film stacked capacitor cells which have been used from the 16M DRAM generation, the cylindrical capacitor cells which have been used from the 64M DRAM generation, the Fin capacitor cells, the thick-film rough-surface capacitor cells, etc. Among these stacked capacitor cells, a structure and a fabrication process of a DRAM
90
having cylindrical capacitor cells will be described referring to
FIGS. 23A
to
32
B.
FIGS. 23A
,
24
A,
25
A,
26
A,
27
A,
28
A,
29
A,
30
A,
31
A and
32
A are partial sectional views showing the memory cell part of the DRAM
90
and
FIGS. 23B
,
24
B,
25
B,
26
B,
27
B,
28
B,
29
B,
30
B,
31
B and
32
B are partial sectional views showing the peripheral circuit part including sense amps, decoders, etc., formed around the memory cell part in the DRAM
90
.
First, in the process step shown in
FIGS. 23A and 23B
, a field oxide film
2
is selectively formed in a P-type silicon semiconductor substrate
1
.
Then P-type impurity ions and N-type impurity ions are selectively implanted by using resist (not shown) as a mask to form a P-type well region
3
in the memory cell part and a P-type well region
3
and an N-type well region
4
in the peripheral circuit part in the P-type silicon semiconductor substrate
1
.
Next, a gate oxide film
5
is formed on the P-type well region
3
and the N-type well region
4
in the part where the field oxide film
2
is not formed and gate electrodes
6
are formed selectively on the gate oxide film
5
. At this time, word lines
61
are formed on the field oxide film
2
in the same process step as the gate electrodes
6
.
Then N-type impurity (As or P) ions are implanted to a low dose (1×10
13
to 1×10
14
cm
−2
) into the P-type well region
3
right under the gate oxide film
5
in the memory cell part by using the gate electrodes
6
as masks to selectively form N-type source/drain regions
71
,
72
,
73
, and N-type source/drain regions
74
,
75
are selectively formed in a similar process in the P-type well region
3
right under the gate oxide film
5
in the peripheral circuit part.
Next, in the process step shown in
FIGS. 24A and 24B
, an oxide film OX
1
is formed all over the surface and resist R
1
is formed except on the P-type well region
3
in the peripheral circuit part, and the oxide film OX
1
is then etched back by using this resist R
1
as a mask to form side wall oxide films
10
on both sides of the gate electrode
6
on the P-type well region
3
in the peripheral circuit part.
Subsequently, by using the gate electrode
6
and the side wall oxide films
10
on the P-type well region
3
in the peripheral circuit part and the resist R
1
as masks, N-type impurity ions are implanted to a high dose (1×10
15
to 4×10
15
cm
−2
) into the N-type source/drain regions
74
and
75
to form N
+
-type source/drain regions
91
and
92
.
Next, after removing the resist R
1
, in the process step shown in
FIGS. 25A and 25B
, resist R
2
is formed except on the N-type well region
4
in the peripheral circuit part and the oxide film OX
1
is etched back by using the resist R
2
as a mask to form side wall oxide films
10
on both sides of the gate electrode
6
on the N-type well region
4
in the peripheral circuit part.
Subsequently, by using the gate electrode
6
and the side wall oxide films
10
on the N-type well region
4
in the peripheral circuit part and the resist R
2
as masks, P-type impurity (B or BF
2
) ions are implanted to a high dose (1×10
15
to 4×10
15
cm
−2
) into the N-type well region
4
to form P
+
-type source/drain regions
81
and
82
.
Next, the resist R
2
is removed, and then as shown in the process step shown in
FIGS. 26A and 26B
, an oxide film is formed all over the surface and an interlayer insulating film
11
is formed by planarization. The interlayer insulating film
11
is referred to as an interlayer insulating film underlying bit lines so that it can be distinguished from other interlayer insulating films.
Next, a bit line contact hole
12
is formed through the interlayer insulating film
11
to reach the N-type source/drain region
72
in the memory cell part.
Next, a polysilicon layer, containing N-type impurities, is formed over the entire surface of the interlayer insulating film
11
, and then the polysilicon layer is removed by CMP (Chemical Mechanical Polishing) except in the bit line contact hole
12
to form a polysilicon plug
13
in the bit line contact hole
12
.
Next, in the process step shown in
FIGS. 27A and 27B
, bit line contact holes
14
are formed through the interlayer insulating film
11
to reach the N
+
source/drain regions
91
and
92
and the P
+
-type source/drain regions
81
and
82
in the peripheral circuit part. Then a metal layer of TiN (titanium nitride) or W (tungsten), or a multi-layered film thereof, is formed all over the interlayer insulating film
11
and the metal layer is then removed by CMP except in the bit line contact holes
14
to form metal plugs
15
in the bit line contact holes
14
.
Next, in the process step shown in
FIGS. 28A and 28B
, a metal layer of TiN or W, or a multi-layered film thereof, is formed all over the interlayer insulating film
11
and patterned by photolithography and etching to form metal bit lines
16
. The metal bit lines
16
are so patterned that they are connected to the polysilicon plug
13
and the metal plugs
15
.
Although the metal bit lines
16
in the peripheral circuit part do not always function only as bit lines, they are so named because they are formed in the same process as the bit lines in the memory cell part. Also, the bit line contact holes
14
are so named because they are connected to the metal bit lines
16
, though they are not always connected to bit lines.
Although not shown in
FIGS. 23B
,
24
B,
25
B,
26
B,
27
B and
28
B, a TG (Transfer Gate) wiring is formed in the peripheral circuit part in the same fabrication process as the word lines
61
(i.e., the gate electrodes
6
), for example. Since the TG wiring is formed in almost the same layer as the gate electrodes
6
, it may be electrically connected with the metal bit lines
16
by using the bit line contact holes
14
.
That is to say, in the process step shown in
FIG. 27B
, a bit line contact hole (almost the same as the bit line contact holes
14
) reaching the TG wiring through the interlayer insulating film
11
may be formed at the same time when forming the bit line contact holes
14
, and then a metal plug
15
is buried also in the bit line contact hole reaching the TG wiring at the same time when the metal plugs
15
are buried in the bit line contact holes
14
.
Next, in the process step shown in
FIGS. 29A and 29B
, an oxide film is formed all over the surface of the
Maldonado Julio J.
Renesas Technology Corp.
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