Recessed drain extensions in transistor device

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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C257SE51005, C257SE51006, C438S482000, C438S485000

Reexamination Certificate

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10967766

ABSTRACT:
A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.

REFERENCES:
patent: 6214679 (2001-04-01), Murthy et al.
patent: 6214736 (2001-04-01), Rotondaro et al.
patent: 6316320 (2001-11-01), Nakahata et al.
patent: 6645835 (2003-11-01), Yamoto et al.
patent: 6878592 (2005-04-01), Besser et al.
patent: 6949482 (2005-09-01), Murthy et al.

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