Recess channel flash architecture for reduced short channel...

Details Recess channel flash architecture for reduced short channel... Recess channel flash architecture for reduced short channel...

2005-11-15

2005-11-15

Le, Thao P. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S301000

Reexamination Certificate

active

06965143

ABSTRACT:
A memory cell with reduced short channel effects is described. A source region and a drain region are formed in a semiconductor substrate. A trench region is formed between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A gate dielectric layer is formed in the trench region of the semiconductor substrate above the recessed channel region and between the source region and the drain region. A control gate layer is formed on the semiconductor substrate above the recessed channel region, wherein the control gate layer is separated from the recessed channel region by the gate dielectric layer.

REFERENCES:
patent: 4256514 (1981-03-01), Pogge
patent: 5773343 (1998-06-01), Lee et al.
patent: 6137132 (2000-10-01), Wu
patent: 6147377 (2000-11-01), Liu
patent: 6153467 (2000-11-01), Wu
patent: 6853587 (2005-02-01), Forbes
patent: 2002/0024092 (2002-02-01), Palm et al.

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