Receiving apparatus, receiving method, and digital PLL circuit

Details Receiving apparatus, receiving method, and digital PLL circuit Receiving apparatus, receiving method, and digital PLL circuit

1997-10-06

1999-06-29

Ghebretinsae, Temesghen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327156, H03D 324

Patent

active

059178736

ABSTRACT:
A PCR is detected from a bit stream by a PCR extracting circuit. When the time reference value is detected, an STC counter counts a clock oscillated by a VCO and compares the value of the STC counter and the value of the PCR. The phase difference is fed back to the VCO through a digital filter. In the control start stage, the gain of the digital filter is designated to a large value. Thus, the phase difference is quickly converged to the allowable difference range. In the lock stage, the gain is designated to a small value. Thus, the control operation is stably performed. In the nearly unlock stage, the gain is designated to a middle value. Thus, the phase difference is quickly pulled to the allowable difference range.

REFERENCES:
patent: 5699392 (1997-12-01), Dokic
patent: 5768326 (1998-06-01), Koshiro et al.

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