Receiving a write request that allows less than one cache line o

Details Receiving a write request that allows less than one cache line o Receiving a write request that allows less than one cache line o

1996-06-05

1999-05-11

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395875, 395306, G06F13/14

Patent

active

059039060

ABSTRACT:
A computer system includes a memory device on the first data bus, a device that initiates on a second data bus a write transaction that can involve less than an entire cache line of data, and a bridge device that automatically converts the write transaction into one that requires an entire cache line of data and delivers the converted transaction to the first data bus.

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