Receiver for clock and data recovery and method for...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Details

C375S371000, C375S354000, C327S001000, C709S248000, C714S012000

Reexamination Certificate

active

07149269

ABSTRACT:
A receiver for clock and data recovery includes n sampling latches (SL1. . . SLn) for determining n sample values (SV1. . . SVn) of a reference signal (Ref2) at n sampling phases (φ1a. . . (φna) having sampling latch inputs and sampling latch outputs. The receiver further includes a phase position analyzer (5) connected to the sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (φ1a. . . φna), if the sample value (SV1. . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (φ1u. . . φnu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1. . . SLn) is provided for generating adjusted sampling phases (φ1a. . . φna) depending on the sampling phases (φ1u. . . φnu) and said adjusting signal (AS).

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patent: WO 00 34178 (2000-06-01), None

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