Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-05-14
2003-03-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C326S093000
Reexamination Certificate
active
06536025
ABSTRACT:
BACKGROUND
This invention is generally related to high speed digital communications over a parallel bus coupled between integrated circuit (IC) functional units or dies of an electrical system, and more particularly to source synchronous transmissions in such systems.
Processor clock speeds in electrical systems are continuing to increase and show no signs of reaching a plateau. As a result, the bit rate in communications between IC functional units and IC dies in the rest of the system are forced to increase to maintain an optimum performance level in the system. One factor that limits the performance of a high speed system is timing variation or ‘skew’, that is a difference in the timing of the occurrence of a particular signal transition, between the actual system and what was expected or designed for the system. Timing variations may be caused by a combination of one or more factors, including those related to the manufacture of the system such as variations in on-die device parameters, the geometry of printed wiring board (PWB) lines, and IC package line length and impedance. Fatal system errors are more likely when timing variations exceed the maximum levels which the system has been designed to tolerate.
As bit rates increase, the maximum amount of timing variation between a received data signal and a distributed, central clock signal of the system decreases. One way to improve the tolerance of a system to timing variation is to use source synchronous transmissions. In such a transmission, the transmitter IC may synchronize each consecutive bit in a driven data signal with a corresponding, separate transition in a driven strobe signal. The data and strobe paths that carry the data and strobe signals between the receiver and the transmitter ICs are designed to be ‘matched’ so that the timing variation between transitions in the data and strobe signals at the receiver are minimized. However, as bit rates continue to increase beyond 500 MHz, the maximum timing variation tolerable by the logic functional circuitry in the receiver IC may be exceeded even by a source synchronous transmission.
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Borkar Shekhar Y.
Haycock Matthew B.
Kennedy Joseph T.
Martin Aaron K.
Mooney Stephen R.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Siek Vuthe
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