Receiver circuitry for receiving reduced swing signals from...

Details Receiver circuitry for receiving reduced swing signals from... Receiver circuitry for receiving reduced swing signals from...

2008-04-21

2010-06-22

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S068000

Reexamination Certificate

active

07741873

ABSTRACT:
A receiver for receiving a reduced swing signal from a transmission channel is disclosed, in which the swing of the reduced swing signal is less than the power supply of the receiver and possibly is less than the power supply of the transmitter. The receiver comprises a level shifter for offsetting the reduced swing signal, and an amplifier which receives both the reduced swing signal and its offset to produce a full swing signal output referenced to the power supply of the receiver. The full swing signal can thereafter be buffered, and eventually can be captured by a clock. Optionally, the disclosed reduced swing receiver also contains calibration circuitry for improving the integrity of the full swing signal output, and in particular for countering the effects of process, and in some embodiments temperature, variations, which alter the characteristics of the transistors which make up the receiver circuitry. More particularly, the calibration circuitry compensates for the unbalanced way in which process and temperature variations impact transistors of differing polarities (e.g., n-type and p-type).

REFERENCES:
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patent: 5754059 (1998-05-01), Tanghe et al.
patent: 6201429 (2001-03-01), Rosenthal
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patent: 7027276 (2006-04-01), Chen
patent: 10-2001-0005093 (2001-01-01), None
Jedec Standard JESD8-13, Scalable Low-Voltage Signaling for 400 mV (SLVS-400) (Oct. 2001).
Mobile Industry Processor Interface (MIPI): “MIPI Alliance Specification for D-PHY,” ver. 0.90.00 (Oct. 8, 2007).
Wong et al.; “A 27-mW 3.6-Gb/s I/O Transceiver;” IEEE Journal of Solid-State Circuits; vol. 39, No. 4; Apr. 2004; pp. 602-612.

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