Receiver circuit of semiconductor memory apparatus

Details Receiver circuit of semiconductor memory apparatus Receiver circuit of semiconductor memory apparatus

2008-07-17

2010-12-14

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S108000, C327S109000, C327S110000, C327S112000, C327S333000

Reexamination Certificate

active

07852131

ABSTRACT:
A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal.

REFERENCES:
patent: 7124221 (2006-10-01), Zerbe et al.
patent: 7176721 (2007-02-01), Ho et al.
patent: 7212580 (2007-05-01), Hietala et
patent: 2009/0058476 (2009-03-01), Oh et al.
patent: 1020040009269 (2004-01-01), None

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