Receiver circuit of semiconductor memory apparatus

Details Receiver circuit of semiconductor memory apparatus Receiver circuit of semiconductor memory apparatus

2008-07-11

2010-06-08

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S191000

Reexamination Certificate

active

07733727

ABSTRACT:
A receiver circuit is described herein, comprising a first data determining unit configured to detect and amplify a voltage level difference between first and second external data and generate first and second sense signals and to generate first internal data in response to the first and second sense signals, a first offset control unit configured to generate first and second offset signals in response to the first and second sense signals, the first and second offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a first code, a second data determining unit configured to detect and amplify the voltage level difference between the first and second external data to generate third and fourth sense signals and to generate second internal data in response to the third and fourth sense signals; and a second offset control unit for generating third and fourth offset signals in response to the third and fourth sense signals, the third and fourth offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a second code, wherein the first data determining unit is configured to determine setup time and hold time of the first internal data in response to the third and fourth offset signals, and wherein the second data determining unit is configured to determine setup time and hold time of the second internal data in response to the first and second offset signals.

REFERENCES:
patent: 5383155 (1995-01-01), Ta
patent: 6301180 (2001-10-01), Sudo et al.
patent: 7093145 (2006-08-01), Werner et al.
patent: 7124221 (2006-10-01), Zerbe et al.
patent: 7126408 (2006-10-01), Zerbe
patent: 7227798 (2007-06-01), Gupta et al.
patent: 7269212 (2007-09-01), Chau et al.
patent: 7286428 (2007-10-01), Baker
patent: 7355914 (2008-04-01), Raszka
patent: 7489588 (2009-02-01), Hanzawa et al.
patent: 7505343 (2009-03-01), Kang
patent: 2006/0256849 (2006-11-01), Tseng et al.
patent: 11027134 (1999-01-01), None
patent: 11-317774 (1999-11-01), None
patent: 2003318726 (2003-11-01), None
patent: 1020070014242 (2007-02-01), None

Affiliated with

Also associated with

Rating

Receiver circuit of semiconductor memory apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Receiver circuit of semiconductor memory apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Receiver circuit of semiconductor memory apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4226442