Receiver circuit for on chip timing adjustment

Details Receiver circuit for on chip timing adjustment Receiver circuit for on chip timing adjustment

2005-09-22

2009-02-03

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C327S153000, C327S158000, C327S166000

Reexamination Certificate

active

07487481

ABSTRACT:
A structure for for maintaining signal integrity between integrated circuits residing on a printed circuit board. The structure has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.

REFERENCES:
patent: 4210828 (1980-07-01), Takaoka et al.
patent: 4993019 (1991-02-01), Cole et al.
patent: 5043596 (1991-08-01), Masuda et al.
patent: 5184027 (1993-02-01), Masuda et al.
patent: 5388060 (1995-02-01), Adams et al.
patent: 5394490 (1995-02-01), Kato et al.
patent: 5525914 (1996-06-01), Cao et al.
patent: 5948115 (1999-09-01), Dinteman
patent: 6043694 (2000-03-01), Dortu
patent: 6323711 (2001-11-01), Truong et al.
patent: 6519104 (2003-02-01), Cloke et al.
patent: 6584031 (2003-06-01), Fujisawa et al.
patent: 6621762 (2003-09-01), Roohparvar
patent: 6662352 (2003-12-01), Nsame et al.
patent: 6665627 (2003-12-01), Jain et al.
patent: 6857089 (2005-02-01), Schaber et al.
patent: 7035611 (2006-04-01), Garlepp et al.
patent: 7051309 (2006-05-01), Crosetto
patent: 2001/0047450 (2001-11-01), Gillingham et al.
patent: 2002/0000855 (2002-01-01), Lee
patent: 2002/0160558 (2002-10-01), Ernst et al.
patent: 2002/0175728 (2002-11-01), DeRyckere et al.
patent: 2002/0184577 (2002-12-01), Chow et al.
patent: 2003/0081709 (2003-05-01), Ngo et al.
patent: 2004/0153267 (2004-08-01), Fishman et al.
patent: 2004/0216024 (2004-10-01), Jin et al.
Hafed et al., “A high-throughput 5 GBPS Timing and Jitter Module Featuring Localized Processing”, Proceedings International, pp. 728-737, 2004.

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