Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-10-11
2002-09-24
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S023000, C326S115000, C327S057000
Reexamination Certificate
active
06456111
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a receiver circuit for a complementary signal and, more particularly, to a receiver circuit having an interface for receiving a complementary signal from a pair of signal transmission lines in a communication system.
(b) Description of the Related Art
A computer network system generally includes a communication system having a transmitter circuit and a receiver circuit for transmission of data between the host computer and each terminal unit. The communication system installed in the computer network system uses a low voltage differential signaling (LVDS) technique wherein transmitted data assumes a complementary current signal, thereby achieving a high-speed data transmission via a pair of signal transmission lines.
FIG. 1
shows a conventional receiver circuit used in a communication system, which is described in Patent Publication JP-A-11-229660. The receiver circuit includes first and second input terminals
13
and
14
connected to a transmitter circuit (not shown) via a pair of signal transmission lines
17
and
18
, a bias terminal
15
maintained at a specified potential, and an output terminal
16
for delivering an output signal.
The transmitter circuit transmits a complementary potential signal to the input terminals
13
and
14
by setting the transmission lines either at a ground level or at a high-impedance state (or floating level) based on the data to be transmitted. In this case, when one of the first and second input terminals
13
and
14
assumes a ground potential, the other of the first and second input terminals
13
and
14
assumes a floating level.
Assuming that the first input terminal
13
assumes a ground potential and the second input terminal
14
assumes a floating level, transistors Qn
1
and Qn
3
are turned on to lower the potential of a node Nb to a low level, whereas transistors Qn
2
and Qn
4
are tuned off to raise the potential of a node Na to a high level.
On the other hand, if the first input terminal
13
assumes a floating level and the second input terminal
14
assumes a ground level, transistors Qn
1
and Qn
3
are turned off to raise the potential of node Nb to a high level, whereas transistors Qn
2
and Qn
4
are turned on to lower the potential of node Na to a low level.
NAND gates
31
and
32
are so connected to form an RS flip-flop for latching a data based on the levels of nodes Na and Nb, and delivers the latched data to the output terminal
16
via an inverter
33
.
The conventional receiver circuit as described above operates on the basis of the constant currents supplied from transistors Qp
1
to Qp
4
, and delivers the output data corresponding to the transmitted complementary signal based on the potentials of nodes Na and Nb.
In the operation of transistors (discharging transistors) Qn
5
and Qn
6
, when transistor Qn
1
or Qn
2
is turned off, the corresponding transistor Qn
5
or Qn
6
passes a current, which is about 10 to 25% of the current when transistor Qn
1
or Qn
2
is turned on, to the ground. This operation allows the receiver circuit to assume a symmetry between the circuit configuration as observed from the first input terminal
13
and the circuit configuration as observed from the second input terminal
14
, thereby achieving a high-speed and stable signal transmission.
In the conventional receiver circuit as described above, however, there is a problem in that the amplitude of the transmitted signal is lowered to reduce the operational margin of the receiver circuit if the ground potential of the transmitter circuit is higher than the ground potential of the receiver circuit due to some reason. This hinders the high-speed and stable signal transmission of the receiver circuit.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the above problem and provide a receiver circuit for use in a communication system, which is capable of achieving a high-speed and stable operation thereof irrespective of a potential difference residing between the ground potential of the receiver circuit and the ground potential of the transmitter circuit.
The present invention provides, in a first aspect thereof, a receiver circuit including: first and second input terminals for receiving a complementary potential signal having a fixed potential level and a floating level; first and second current sources each having first and second terminals, the first terminals of the first and second current sources being connected together; first and second switching transistors each connected between a corresponding one of the first and second input terminals and the second terminal of a corresponding one of the first and second current sources; a current detection transistor connected between the first terminals of the first and second current sources and a first power source line; a voltage control unit for applying a potential corresponding to a current detected by the current detection transistor to gates of the first and second switching transistors; and an RS latch circuit for receiving potentials of drains of the first and second switching transistors at a set input and a reset input, respectively, of the RS latch circuit.
The present invention provides, in a second aspect thereof, a receiver circuit including: first and second input terminals for receiving from first and second transmission lines a complementary potential signal having a fixed potential level and a floating level; first and second current supplying units including first and second switching transistors, respectively, for supplying currents in the form of a complementary current signal corresponding to the complementary potential signal through the first and second terminals to the first and second transmission lines; an RS latch circuit for latching a set signal and a reset signal corresponding to the complementary current signal; a current detection unit for detecting a sum of currents supplied from first and second current supplying unit to output a current detection signal; and a potential control unit for controlling gate potentials of the first and second switching transistors based on the current detection signal for implementing a negative feedback loop.
In accordance with the receiver circuits of the present invention, since the current fluctuation due to the fluctuation of the complementary potential signal can be suppressed by the voltage control unit or the negative feedback loop, the potential difference between the ground potential of the transmitter circuit and the ground potential of the receiver circuit does not degrades the operational margin of the receiver circuit and thus does not hinder the high-speed and stable operation thereof.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
REFERENCES:
patent: 6060912 (2000-05-01), Opris et al.
patent: 6184722 (2001-02-01), Hayakawa
patent: 11-229660 (1999-08-01), None
Chang Daniel D.
NEC Corporation
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