Receiver circuit

Details Receiver circuit Receiver circuit

2008-07-08

2008-07-08

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Reliability

Fail-safe

C326S009000

Reexamination Certificate

active

11653340

ABSTRACT:
In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

REFERENCES:
patent: 4446437 (1984-05-01), Rinaldi
patent: 5301171 (1994-04-01), Blow et al.
patent: 6320406 (2001-11-01), Morgan et al.
patent: 6781456 (2004-08-01), Pradhan
patent: 61-193541 (1986-08-01), None
patent: 05-037573 (1993-02-01), None
patent: 10-200450 (1998-07-01), None
patent: 2001-237681 (2001-08-01), None
Japanese Office Action, with English Translation, issued in corresponding Japanese Patent Application No. JP 2002-346153, mailed on Jan. 29, 2008.

Affiliated with

Also associated with

Rating

Receiver circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Receiver circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Receiver circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3925381