Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-07-27
2003-11-11
Verbrugge, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000
Reexamination Certificate
active
06647465
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a parallel processor. More particularly, this invention relates to architecture of a real time parallel processor system for transferring common information among parallel processors to a cache memory system of each processor and utilizing the common information, and method of constituting each constituent means into LSI architecture.
The specifications of the patent applications Ser. Nos. 08/701,789 and 09/165,200 filed by M. Kametani on Aug. 26, 1996 and Oct. 2, 1998 and published as U.S. Pat. Nos. 5,960,458 and 6,161,168 on Sep. 28, 1999 and Dec. 12, 2000, respectively, disclose a shared memory system.
An example of a general-purpose multi-processor such as a main frame that includes a common main memory having a caching function of common information can be cited as a principal prior art technology.
U.S. Pat. No. 5,604,882 and JP-A-9-185547 disclose primarily coherence control means of common information on a cache memory of each processor element that constitutes a multiprocessor. The references describe a system for nullifying a directory (in a tag memory) for cache memory of each corresponding processor when the content of the common main memory is changed, and a method for directly exchanging replace information among cache memories.
JP-A-1-145746 and JP-A-7-13863 describe a system which uses RAM having two ports for a cache memory and a tag memory, monitors a write cycle in which a common main memory system connected to a common bus (or a system bus) is re-written, and re-writes the cache memory by use of the information of the write cycle through the other port in parallel with the cache memory access of the processor that is executed by use of one of the ports.
These prior art technologies are based on the premise that one common main memory system on the common bus is directly shared by a plurality of processors. The common memory system is generally used for residence of an OS common to each processor, sharing of status information for common control and information transfer among the processors.
When coherence control is executed in accordance with the prior art technologies, a high real time communication capacity capable of quickly communicating and converting large quantities of information among processors is necessary so that even when common information is incessantly changed in response to information generated by other processors and in response to external real time information, each processor can handle large quantities of common information on the real time basis. In a multi-processor of the type for which a high-speed processing capacity is required and in which processors are densely coupled, or in a high-speed real time parallel processor which is required to exhibit quick response and to execute a processing at a predetermined high processing speed, a critical problem develops to keep such performance. In other words, a replace operation of common information frequency occurs from a common memory system to a cache memory system in such a high-speed system, and large quantities of re-write processing of internal information of the common memory system occur from each processor, too. Therefore, conflict occurs on the common bus or between the common bus and a monitor bus of the common bus write information due to these access operations, thereby inviting a critical problem of the loss of the processing capacity (about overhead) such as a temporary stop of the operation of the processor, a remarkable drop of the overall operation speed and an irregular occurrence of the extreme drop of performance that impedes to keep real time performance. To keep real time performance, therefore, it is generally more suitable in many cases not to cache the common information in such a system.
The prior art technologies using a cache memory and a tag memory of RAM having 2 ports may seem capable of avoiding the conflict. However, when the number of times of the replace operations from the main memory through the common bus increases as in the problem discussed hereby, this increase synergistically affects the replace operations by other processors, so that the common bus monitor operation for keeping coherence is relatively neglected and a large drop of efficiency occurs.
In other words, it is mainly when the processor primarily executes the processing using the cache memory (a processing primarily directed to process data on the cache memory in a main frame, a work station, a personal computer, etc) that the effect can be obtained. The effect at this time remains only that the cache memory access conflict can be avoided between the processor side and the common bus monitor side. Therefore, the prior art does not yet relate to the technology for securing sufficient real time performance.
To achieve a higher operation speed, it is essential to fabricate each constituent means into LSI architecture, but the prior art examples do not describe a technology satisfying such a requirement.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a processor system having by far higher performance than the prior art systems, that solves the problems described above, prevents the drop of performance resulting from various address conflicts, can shorten latency and has high cost performance owing to LSI architecture.
The problems described above can be solved by a processor connected to at least one processor through a common bus, for executing cache control, comprising CPU; a cache memory; a tag memory connected to the cache memory, for holding address information of cache data; a resource for holding data common to at least one processor; a write port provided to the resource and connected to the common bus; and a comparator for comparing address information of the tag memory with an access address from the CPU and outputting coincidence information to the cache memory; wherein a local bus for gaining access to the resource from the processor is connected to a read port provided to the resource.
The cache memory may have a write/read port connected to an internal bus from the CPU and a write port for accepting the common data from at least one processor through an external bus connected to the common bus.
The comparator described above includes a first comparator connected to the tag memory, for comparing the access address from the CPU with the address information of the tag memory and giving an enable signal for activating the write/read port of the cache memory; and a second comparator connected to the tag memory, for comparing the access address from at least one processor with the address information of the tag memory, and giving an enable signal for activating the write port of the cache memory, wherein the first and second comparators are operable in parallel with each other by one reference clock.
In a system wherein a plurality of processors exist and each processor executes a parallel processing or a distributed processing while exchanging information among them by a common system for holding common information among the processors, the present invention relates to means, systems and methods for executing coherence control of the common information between cache memories of the processors while the information inside the common system is replaced into, and processed by, a cache memory system inside the processor.
REFERENCES:
patent: 5522058 (1996-05-01), Iwasa et al.
patent: 5659714 (1997-08-01), Yoshida
Funatsu Terunobu
Kametani Masatsugu
Umekita Kazuhiro
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Verbrugge Kevin
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