Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2004-06-21
2009-08-11
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S724000, C714S712000, C714S734000, C365S201000
Reexamination Certificate
active
07574634
ABSTRACT:
A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is disclosed. One or more test mode related signals, which include on-die signals and other relevant information, may be transferred from the integrated circuit of the electronic device to an external processor using the device's ODT circuit instead of the output data signal driver circuit. Therefore, no capacitive loading of output drivers occurs during test mode operations. Thus the speed of the output data path (i.e., the circuit path propagating non-test mode related signals from the electronic device to other external units in the system) is not affected by test mode operations, allowing a system designer to increase the speed of the data output path as much as desired. Further, deterioration in the quality of signals output from the output drivers is also avoided. Also, the use of a minimal number of logic gates along with the existing ODT circuits to perform transmission of test mode related signals substantially maximizes chip real estate utilization without waste. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
REFERENCES:
patent: 4435803 (1984-03-01), Das et al.
patent: 6335632 (2002-01-01), Hui
patent: 6535047 (2003-03-01), Mughal et al.
patent: 6714038 (2004-03-01), Lee et al.
patent: 6741095 (2004-05-01), Abrosimov et al.
patent: 6762620 (2004-07-01), Jang et al.
patent: 6809546 (2004-10-01), Song et al.
patent: 6842035 (2005-01-01), Kurts et al.
patent: 6859059 (2005-02-01), Rohrbaugh et al.
patent: 6924660 (2005-08-01), Nguyen et al.
patent: 7020818 (2006-03-01), Dour et al.
patent: 7034565 (2006-04-01), Lee
patent: 7034567 (2006-04-01), Jang
patent: 7092299 (2006-08-01), Kwak et al.
patent: 7151390 (2006-12-01), Nguyen et al.
patent: 7170313 (2007-01-01), Shin
patent: 7227377 (2007-06-01), Kurts et al.
patent: 7239560 (2007-07-01), Lee et al.
patent: 7245140 (2007-07-01), Sunwoo et al.
patent: 2002/0188898 (2002-12-01), Tsuji
patent: 2004/0141391 (2004-07-01), Lee et al.
patent: 2006/0262604 (2006-11-01), Johnson
patent: 2007/0113209 (2007-05-01), Park et al.
DDR2, The Next-Generation Synchronous Dram, available at http://www.elpida.com/pdfs/E0294E30.pdf on Mar. 8, 2004, 3 pgs.
designline, vol. 12, Issue 2, available at ://download.micron.com/pdf/pubs/designline/dl3Q03.pdf on Mar. 8, 2004, 16 pgs.
Micron/On-Die Termination/Thermal Considerations TN-44-02 available at http://download.micron.com/pdf/technotes/TN4402.pdf on Mar. 8, 2004, 7 pgs.
DRAM Memory System: Lecture 12, available at http://www.ee.umd.edu/courses/enee759h.S2003/lectures/Lecture12.pdf on Mar. 8, 2004, 17 pgs.
Jones Day
Merant Guerrier
Micro)n Technology, Inc.
Pencoske Edward L.
Trimmings John P
LandOfFree
Real time testing using on die termination (ODT) circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Real time testing using on die termination (ODT) circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Real time testing using on die termination (ODT) circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4126368