Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2001-06-05
2004-03-30
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06715123
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a real-time recording system, and more particularly, to a real-time recording system that records image data or the like in real-time to a recording medium such as a DVD-RAM.
When a real-time recording system records image data recorded by a video camera to a recording medium in real-time, the recording system receives the image data and at the same time successively writes the received image data to the recording medium. The recording system performs an error correction process on the write data to increase the reliability of the write data. The recording system has a central processing unit, such as an MPU, to control the recording of the image data. The load applied to the central processing unit has increased in recent years. Thus, it has become required that the load on the central processing unit be decreased.
FIG. 1
is a schematic block diagram of a prior art real-time recording system
50
. The recording system
50
records image data to a DVD-RAM
7
in real-time. Further, the recording system
50
has a control unit
1
, an MPU
5
, and a memory
6
.
The control unit
1
includes an error correcting code (ECC) circuit
2
, a formatter circuit
3
, and a bus
4
. The bus
4
connects the ECC circuit
2
and the formatter circuit
3
. The ECC circuit
2
and the formatter circuit
3
are also connected to the memory
6
. The bus
4
is connected to the MPU
5
. The formatter circuit
3
is connected to the DVD-RAM
7
.
When the real-time recording system
50
records image data to the DVD-RAM
7
, data is transferred via a host interface and temporarily stored in the memory
6
. The data is sequentially stored in partitioned areas m, m+1, . . . , of the memory
6
. In each of the areas m, m+1, . . . , data is stored in block units. Each block of data includes
16
sectors.
The data stored in the memory
6
is transferred to the ECC circuit
2
. A data identification (ID) is added to each sector. To increase data reliability, the data undergoes a scramble process and an error detecting code (EDC) and ECC error correction process. The processed data is stored in the memory
6
again. The error correction process is performed on each block of data.
Then, the formatter circuit
3
reads the processed data from the memory
6
one block at a time and reads a header ID from the DVD-RAM
7
. The formatter circuit
3
modulates the data and writes the modulated data to an area of the DVD-RAM
7
corresponding to the header ID.
If the formatter circuit
3
is unsuccessful in reading the header ID that corresponds to area N of the DVD-RAM
7
(
FIG. 2
) in which data is to be written, the formatter circuit
3
detects a header error and generates an error signal. The error signal is sent to the MPU
5
.
The MPU
5
provides the error signal to the ECC circuit
2
and instructs the next data that is to be written. The ECC circuit
2
adds 10 h (hexadecimal) to the value of the ID of the data at which the write error occurred and performs the ECC process on the error data again. The reprocessed data is stored again in the memory
6
.
When, for example, write data of a block that includes a write error is stored in area r, the reprocessed data is stored in area r+1.
The reprocessed data stored in area r+1 is block-slipped and written to the DVD-RAM
7
at area N+10 h, which is the area next to area N.
In the real-time recording system
50
, when a read error of the header ID occurs, the MPU
5
recognizes the read error and instructs the ECC circuit
2
of the write data that is to be generated next. The MPU
5
recognizes the area of the memory
6
in which the write data generated by the ECC circuit
2
has been stored. This increases the load applied to the MPU
5
and decreases the operating speed of a DVD recording/reproduction device, which includes peripheral devices controlled by the MPU
5
.
Further, the re-writing is controlled by means of the MPU
5
. This increases the time required to generate the re-write data.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a real-time recording system that decreases the load applied to a central processing unit, which controls recording.
To achieve the above object, a first perspective of the present invention is a recording system for receiving input data and simultaneously recording the input data to a recording medium. The system includes a memory for storing the input data. An error correction circuit is connected to the memory for generating write data from the input data and storing the generated write data in the memory. A formatter circuit is connected to the memory and the error correction circuit for reading the write data stored in the memory and writing the read write data to the recording medium in real-time. The error correction and formatter circuits are controlled for the generation of the write data with the error correction circuit and the writing operation with the formatter circuit by a plurality of control signals. The plurality of control signals are transferred between the error correction circuit and the formatter circuit.
A second perspective of the present invention is a method for recording data in a recording system including a memory for storing input data, an error correction circuit connected to the memory for generating write data from the input data and storing the generated write data in the memory, and a formatter circuit connected to the memory and the error correction circuit for reading the write data stored in the memory and writing the read write data to a recording medium in real-time. The method includes generating the write data with the error correction circuit by transferring a plurality of control signals between the error correction circuit and the formatter circuit, and writing the write data to the recording medium with the formatter circuit according to the plurality of control signals.
Other perspectives and advantages of the present invention will become apparent from the following detailed description and claims, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 4455655 (1984-06-01), Galen et al.
patent: 5610929 (1997-03-01), Yamamoto
patent: 5740358 (1998-04-01), Geldman et al.
patent: 6009550 (1999-12-01), Gosula et al.
patent: 6401168 (2002-06-01), Williams et al.
patent: 6530000 (2003-03-01), Krantz et al.
Kitamura Yoshitaka
Yamawaki Masashi
De'cady Albert
Fujitsu Limited
Staas & Halsey , LLP
Torres Joseph D.
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