Real-time reconfigurable vision computing system

Details Real-time reconfigurable vision computing system Real-time reconfigurable vision computing system

1999-04-01

2001-06-05

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000

Reexamination Certificate

active

06242944

ABSTRACT:

BACKGROUND OF THE INVENTION
Processing of video requires processing of a large amount of information. Typical video has a resolution of 640×480 pixels at 30 frames/sec. This requires processing 9.2 M-bytes/sec for monochrome video, or 27.6 M-bytes/sec for color signal. This large amount of information has often been handled by a special kind of processor. Different kinds of processors have been used to process this large amount of information.
A single instruction multiple data processor is one example of a massively-parallel supercomputer that can be used for this purpose. Application specific integrated circuits “ASICs” have also been used. Both of these technologies have their own host of advantages and disadvantages.
Field-programmable gate arrays (FPGA's) can also be used for processing video. A field-programmable gate array includes a large number of configurable logic blocks (CLB's) and a programmable mesh of interconnections. Static memory cells, which are scattered across the gate array are used to specify the logic of the blocks and the interconnection pattern.
SUMMARY OF THE INVENTION
The present system recognizes that FPGA's can be advantageously used in vision systems of this type. According to the present system, a special memory interface is described which uses FPGAs in a reconfigurable computer system that is optimized for image processing. The FPGAs are used with external components, preferably fast static random access memory (“SRAM”). The bandwidth is increased by sharing interface lines.


REFERENCES:
patent: 5760607 (1998-09-01), Leeds et al.
patent: 5787007 (1998-07-01), Bauer
patent: 5804986 (1998-09-01), Jones
patent: 6055594 (2000-04-01), Lo et al.

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