Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2007-10-16
2007-10-16
Trujillo, James K. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
Reexamination Certificate
active
10913964
ABSTRACT:
An interrupt timer module comprises a prescale counter (PSC) incremented by a real-time interrupt clock signal (RTICLK), a prescale compare value register (CVR) storing a configurable value (PCV), a comparator comparing the current count of the prescale counter (PSC) with the stored configurable value (PCV), a free running counter (FRC) incremented by a match from the comparator, and a plurality of interrupt generation units (IGU0, IGU1, IGU2) Each interrupt generation unit (IGU0, IGU1, IGU2) comprises a compare value register (CVR0, CVR1, CVR2) storing a compare value and a comparator comparing the compare value from the respective compare value register with the current count of the free running counter providing one or both of an interrupt signal (INT0, INT1, INT2) and a direct memory request signal (DMAREQ0, DMAREQ1, DMAREQ2) upon a match.
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Messmer, Hans-Peter;PC-Hardwarebuch, Aufbau, Funktionsweise, Programmierung Ein Handbuch Nicht Nur Fur Profis, 5.Auflage, no English translation, 15 pgs.
Fernandez Neomi
Noha Frank
Brady W. James
Chang Eric
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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