Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt prioritizing
Reexamination Certificate
2006-02-09
2008-12-30
Knoll, Clifford H (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt prioritizing
C710S260000, C710S240000
Reexamination Certificate
active
07472214
ABSTRACT:
A processor context stored in a stack area at a time of an interrupt occurrence is saved in a context saving area of an ICB corresponding to an ISR that is interrupted. The ISR corresponding to the interrupt is set to an execution-waiting state. An ICB having a highest priority from among the ICBs that are set to the execution-waiting state is selected. A processor context saved in a context saving area of the selected ICB is stored in the stack area. An ISR corresponding to an ICB selected by an interrupt return command is executed.
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Inoue Teiichiro
Iwahashi Masami
Kawakami Toshihiro
Nankaku Shigeki
Buchanan & Ingersoll & Rooney PC
Huynh Kim T
Knoll Clifford H
Mitsubishi Denki & Kabushiki Kaisha
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