Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
1999-07-21
2004-07-13
Mehta, Bhavesh M. (Department: 2621)
Image analysis
Applications
Manufacturing or product inspection
C382S224000, C382S305000, C700S110000, C702S035000
Reexamination Certificate
active
06763130
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for identifying the causes of defects on the surface of a semiconductor substrate. The invention has particular applicability for in-line inspection of semiconductor wafers during manufacture of high-density semiconductor devices with submicron design features.
BACKGROUND ART
Current demands for high density and performance associated with ultra large scale integration call for submicron features, increased transistor and circuit speeds and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
Conventional wafer fabrication process control techniques employ cassettes that each transport a plurality of wafers, each cassette typically carrying a bar code label and/or other form of identification, including wafer identification. After the completion of each process step (e.g., oxide growth, etch, clean, sputter, etc.), information related to the cassette and the “last visited tool”; i.e., the particular oven, etcher, cleaner, polishing machine, etc. used in processing the cassette, is entered into a computer software-implemented database system known as a “manufacturing execution system” (MES). Such information includes cassette identification information, parameters related to the cassette and wafers, and process parameters used at the last visited tool. Thus, the MES tracks the completed process steps, the tools at which the process steps were performed, and the wafers on which the process steps were performed.
After the completion of a series of process steps, and/or after the completion of a critical process step, such as formation of a complex photoresist mask, a number of the wafers in a cassette are inspected, typically at a stand-alone inspection tool, per instructions from the MES. At the inspection tool, the surface of the wafer to be inspected is scanned by a high-speed inspection device; for example, an opto-electric converter such as a CCD (charge-coupled device) or a laser. Typically, the inspection tool then informs the MES that it has completed its inspection. Statistical methods are thereafter employed by the inspection tool to produce a defect map showing suspected locations on the wafer having a high probability of a defect. If the number and/or density of the potential defects reach a predetermined level, an alarm is sounded, indicating that a more detailed look at the potential defect sites is warranted. A review of the potential defect sites is then conducted using the defect map, either at the inspection tool or at a separate stand-alone review station, typically by comparing images of suspected defect sites with reference images to positively determine the presence of a defect, and then analyzing the images to determine the nature of the defect (e.g., a defective pattern, a particle, or a scratch) and its cause.
In current “state of the art” wafer processing facilities, process data from the MES, and inspection and review results from the inspection tools and review stations, are periodically downloaded to another stand-alone computer softwareimplemented system called a “yield management system” (YMS), which employs statistical process control methods to monitor process quality. If the YMS determines that the process is performing outside predetermined control limits, it generates data, such as a list of tools visited by wafers exhibiting defects and the process parameters used at those tools, which are helpful in diagnosing processing problems. The user may then analyze this data to isolate the causes of the defects.
Disadvantageously, the YMS generates and reports its findings “off-line”; i.e., physically remote from the wafer processing tools and inspection tools, and remote in time from when the processing took place. Typically, communication between the MES and the YMS occurs only once or twice a day and, therefore, data from the YMS reaches the user many hours after the wafer has visited the process and inspection tools. Because the user does not receive YMS data in “real time”; i.e., at the time of wafer inspection when the user discovers that defects are occurring, the user does not have the benefit of this extremely valuable information when it is most needed; i.e., when making on-the-spot process adjustments or fault diagnoses.
There exists a need for a methodology for in-process inspection of semiconductor wafers that provides information in real time relating to the tools visited by the wafers and the process parameters used at those tools in order to identify processes causing defects, thereby enabling early corrective action to be taken. This need is becoming more critical as the density of surface features, die sizes, and number of layers in devices increase, requiring the number of defects to be drastically reduced to attain an acceptable manufacturing yield.
SUMMARY OF THE INVENTION
An advantage of the present invention is the ability to automatically retrieve information relating to the tools visited by a semiconductor wafer at a wafer inspection tool at the time of inspection of the wafer, thereby enabling efficient identification of process problem areas.
According to the present invention, the foregoing and other advantages are achieved in part by a method of inspecting a semiconductor wafer, which method comprises subjecting the wafer to a plurality of processing steps using a plurality of processing tools, each of the processing tools respectively associated with a different tool identifier and set of process parameters, and storing the tool identifiers and the set of process parameters. The wafer is then inspected for defects with an inspection tool and a list of the tool identifiers generated, using the inspection tool. The user of the present invention can then request a display of the set of process parameters associated with one of the listed tool identifiers.
Another aspect of the present invention is an apparatus for carrying out the steps of the above method.
A further aspect of the present invention is a computer-readable medium bearing instructions for inspecting a semiconductor wafer, which wafer has been subjected to a plurality of processing steps using a plurality of processing tools, each of the processing tools respectively associated with a different tool identifier, the instructions, when executed, being arranged to cause one or more processors to perform the steps of receiving the tool identifiers; inspecting the wafer for defects; and generating a list of the tool identifiers.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
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pat
Maimon Amotz
Somekh Sasson
Applied Materials Inc.
Chawan Sheela
McDermott & Will & Emery
Mehta Bhavesh M.
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