Real-time connection error checking method and process

Details Real-time connection error checking method and process Real-time connection error checking method and process

2001-08-29

2003-10-28

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06640329

ABSTRACT:

TECHNICAL FIELD
This invention relates to connection error checking which occurs during circuitry design.
BACKGROUND
Integrated circuits typically include various combinational elements (e.g., AND gates, OR gates, NAND gates, XOR gates, etc.) and state elements (e.g., latches, flip-flops, etc.) in their design. Each of these combinational and state elements are discrete elements that the engineer places into the circuit design.
As integrated circuit designs get increasingly complex, engineers need enhanced tools to aid them in the design process. The design process for a semiconductor chip can typically be broken down into subtasks (i.e., design, capture, documentation, compilation, and debug). One typical way to design a complex semiconductor chip would be to have an architecture team and an implementation team. An architecture team provides various models (i.e., a specification and a object-based (e.g., C++) model) of the design to the implementation team. The implementation team tests and simulates the circuit using various tools (e.g., Synopsis
VCS Verilog Simulator, etc.). Any resulting bugs/errors can be collected in a list that is used by the architecture team to modify the circuit design. The modified design can then be given back to the implementation team for further testing.


REFERENCES:
patent: 5128871 (1992-07-01), Schmitz
patent: 5220512 (1993-06-01), Watkins et al.
patent: 5258919 (1993-11-01), Yamanouchi et al.
patent: 5506788 (1996-04-01), Cheng et al.
patent: 5513119 (1996-04-01), Moore et al.
patent: 5553002 (1996-09-01), Dangelo et al.
patent: 5629857 (1997-05-01), Brennan
patent: 5666289 (1997-09-01), Watkins
patent: 5828581 (1998-10-01), Matumura
patent: 5852564 (1998-12-01), King et al.
patent: 5889677 (1999-03-01), Yasuda et al.
patent: 5892678 (1999-04-01), Tokunoh et al.
patent: 5933356 (1999-08-01), Rostoker et al.
patent: 5963724 (1999-10-01), Mantooth et al.
patent: 6044211 (2000-03-01), Jain
patent: 6053947 (2000-04-01), Parson
patent: 6066179 (2000-05-01), Allan
patent: 6106568 (2000-08-01), Beausang et al.
patent: 6117183 (2000-09-01), Teranishi et al.
patent: 6120549 (2000-09-01), Goslin et al.
patent: 6132109 (2000-10-01), Gregory et al.
patent: 6135647 (2000-10-01), Balakrishnan et al.
patent: 6152612 (2000-11-01), Liao et al.
patent: 6205573 (2001-03-01), Hasegawa
patent: 6219822 (2001-04-01), Gristede et al.
patent: 6233540 (2001-05-01), Schaumont et al.
patent: 6233723 (2001-05-01), Pribetich
patent: 6236956 (2001-05-01), Mantooth et al.
patent: 6260179 (2001-07-01), Ohsawa et al.
patent: 6272671 (2001-08-01), Fakhry
patent: 6298468 (2001-10-01), Zhen
patent: 6311309 (2001-10-01), Southgate
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 6366874 (2002-04-01), Lee et al.
patent: 6378115 (2002-04-01), Sakurai
patent: 6401230 (2002-06-01), Ahanessians et al.
patent: 6449762 (2002-09-01), McElvain
patent: 6457164 (2002-09-01), Hwang et al.
patent: 6477683 (2002-11-01), Killian et al.
patent: 6477689 (2002-11-01), Mandell et al.
patent: 6480985 (2002-11-01), Reynolds et al.
patent: 6487698 (2002-11-01), Andreev et al.
patent: 6505341 (2003-01-01), Harris et al.
patent: 6519755 (2003-02-01), Anderson
patent: 2001/0018758 (2001-08-01), Tanaka et al.
patent: 2002/0023256 (2002-02-01), Seawright
patent: 2002/0042904 (2002-04-01), Ito et al.
patent: 2002/0046386 (2002-04-01), Skoll et al.
patent: 2002/0049957 (2002-04-01), Hosono et al.
patent: 2002/0166100 (2002-11-01), Meding
patent: 2003/0005396 (2003-01-01), Chen et al.
patent: 2003/0016206 (2003-01-01), Taitel
patent: 2003/0016246 (2003-01-01), Singh
Renoir—Mentor Graphics, www.mentor.com as of 1999.
Foley et al., “An Object Based Graphical User Interface for Power Systems”, IEEE Transactions on Power Systems, vol. 8, No. 1, Feb. 1993, pp. 97-104.
Pedram et al., “Floorplanning with Pin assignment”, 1990 IEEE International Conference on Computer-Aided Design, Nov. 11, 1990, pp. 98-101.
Renoir, HDL Design Datasheet, Mentor Graphics, 1-8, 1999.
Mentor Graphics Corporation, RenoirTMWith HDL2GraphicsTM, pp. 1-6, 1998, Oregon.
Mentor Graphics Corporation, Renoir HDL Design Datasheet, pp. 1-2, 1999, Oregon.
Computer Design, “After Hard Knocks, Cycle-Based Stimulators Stand Their Ground”. http://www.computer-design.com/Editorial/1996/10/ASIC/after.html, accessed on Aug. 23, 2001, pp. 1-5.

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