Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing extended or expanded memory
Patent
1997-04-25
1999-11-02
Cabeca, John W.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing extended or expanded memory
711208, 711209, 711212, 712227, G06F 1206
Patent
active
059788828
ABSTRACT:
Flat-model, 32-bit, real-mode execution may be obtained in an INTEL.TM. X86-compatible processor of a computer to increase address space, while handling interrupts transparently. A protected-mode operating system is not required. A LOADALL instruction available to an operating system may load hidden cache descriptor registers of a processor with the base addresses, segment limits, and other attributes consistent with 32-bit, real-mode operation to provide 32-bit addressing. Interrupts, would normally interfere with the contents of the hidden cache descriptor registers. A new interrupt vector table is provided, with each new vector therein pointing to one of the new interposer routines provided. Upon receipt of an interrupt, a new interrupt vector points to an interposer routine, which saves the state of the hidden cache descriptor registers. The interposer routine then simulates the interrupt to an appropriate interrupt service routine by vectoring through the old or original interrupt vector table to the interrupt service routine. After its execution, the interrupt service routine provides an interrupt return to the calling interposer routine. The interposer routine then restores the state of the hidden cache descriptor registers to the 32-bit, flat-model execution state. The interposer routine may then provide its own interrupt return, rendering its own operation transparent to both the incoming interrupt and the execution conforming thereto.
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Cabeca John W.
Novell Inc.
Tzeng Fred F.
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