Reading circuit for reading a memory cell

Details Reading circuit for reading a memory cell Reading circuit for reading a memory cell

2006-05-02

2006-05-02

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189050, C365S189011, C365S185210

Reexamination Certificate

active

07038936

ABSTRACT:
A reading circuit comprises a first and second cascode circuit and a first and second current mirror. The first cascode circuit can be connected to a bit line of a memory cell and the second cascode circuit can be connected to a reference bit line of a reference cell. The first output terminals of the first and second cascode circuits are connected to first terminals of the first and second current mirrors, respectively. The second output terminals of the first and second cascode circuits are connected to the second terminals of the second and first current mirrors, respectively. A tri-state buffer is coupled between the second terminals of the first and second current mirrors said buffer having bit invert capabilities.

REFERENCES:
patent: 5563826 (1996-10-01), Pascucci et al.
patent: 6205070 (2001-03-01), Seevinck et al.
patent: 6359808 (2002-03-01), Chen et al.
patent: 0747903 (1996-12-01), None
patent: 0747903 (1996-12-01), None

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