Reading circuit for an integrated semiconductor memory device

Details Reading circuit for an integrated semiconductor memory device Reading circuit for an integrated semiconductor memory device

1995-03-22

1997-05-06

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Differential sensing

3651852, 36518521, 36518909, G11C 702

Patent

active

056277903

ABSTRACT:
A device including a load connected by a selection circuit to a number of bit lines, and a load connected to a reference cell, for detecting the current in the selected bit line and in the reference cell. The load connected to the bit lines comprises a transistor, and the reference load comprises two current paths, each formed by one transistor. One of the two transistors is diode-connected, and the other is switchable by a switching network connected to the gate terminal of the respective transistor, for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.

REFERENCES:
patent: 5142495 (1992-08-01), Canepa
patent: 5293345 (1994-03-01), Iwahashi
Atsumi et al, "Fast Programmable 256K Read Only Memory with On-Chip Test Circuits", IEEE Transactions on Electron Devices, vol. Ed-32, No. 2, Feb. 1985, New York, pp. 502-507.

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