Reading a selected register in a series of computational...

Details Reading a selected register in a series of computational... Reading a selected register in a series of computational...

2005-01-11

2005-01-11

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Processing control for data transfer

C712S218000, C711S167000

Reexamination Certificate

active

06842851

ABSTRACT:
A system and method for reading register contents from a computational pipeline having a plurality of computational units. The system includes a readback bus and a read control unit. The readback bus has a plurality of logic units coupled in a series. Each logic unit couples to a corresponding one of the computational units. The read control unit couples to each of the computational units through a corresponding load line, and is configured to assert a load signal on one of the load lines in response to a register read request. Each of the computational units is configured to transmit a data value from a selected register onto the readback bus in response to detecting an assertion of the load signal on its corresponding load line.

REFERENCES:
patent: 6105123 (2000-08-01), Raje
patent: 6567335 (2003-05-01), Norman et al.

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