Read/write timing calibration of a memory array using a row...

Details Read/write timing calibration of a memory array using a row... Read/write timing calibration of a memory array using a row...

2001-05-08

2004-07-13

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S100000, C702S089000, C713S401000, C713S503000

Reexamination Certificate

active

06763444

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit memory storage devices. Specifically, the present invention relates to a method for performing read/write timing calibration of a memory array, such as a dynamic random access memory array and, specifically, to a method of conducting read/write timing calibration of a memory array using a row or a redundant row.
2. State of the Art
A conventional computer system typically includes a processor coupled to one or more memory devices via a memory controller. During operation of such a computer system, the processor regularly exchanges information—i.e., data bits—with the memory devices. Generally, the processor is capable of processing information at a rate greatly exceeding the rate at which the memory devices are capable of transmitting information to and from the processor. Thus, in conventional computer systems, the maximum speed at which the processor can operate is restricted, not by the processor's inherent processing limitations, but by the rate at which data can be written to the memory devices and the rate at which data can be read from the memory devices.
A conventional memory device, such as a dynamic random access memory (“DRAM”) device, typically includes a memory array comprising a plurality of memory cells arranged in rows and columns. Generally, to write a data bit into a specified memory cell of the memory array, the memory controller provides the data bit to the memory device in response to an internal clock signal and the data bit is retained in the memory device at an input buffer. In response to a data clock signal provided to the memory device by the memory controller, the data bit is latched into the memory array. For reliable transfer of data to the memory array, there must be a sufficient time delay between the internal clock of the memory controller and the data clock signal, such that sampling of the data bit at the input buffer occurs during a time window in which that data bit is valid—i.e., the data valid window. Similarly, to read a data bit out of a specified memory cell of the memory array, the data bit is latched from the memory array to an output buffer in response to a data clock signal provided to the memory device by the memory controller. Subsequently, the data bit is latched into the memory controller in response to the memory controller's internal clock. Again, to insure that the data bit is sampled by the memory controller during its data valid window, a sufficient time delay between the data clock signal and the internal clock signal of the memory controller must be provided.
Although memory architectures having the ability to compensate for the slower operating speed of the memory devices—by using, for example, cache memory—are known in the art, memory device manufacturers are under increasing pressure to produce memory devices capable of operating at ever-increasing speeds, or clock rates, especially in light of high-frequency processors now available in the market. Thus, memory device manufacturers are now producing memory devices capable of operating at clock rates up to 500 MHz and higher. One problem encountered by memory device manufacturers in regard to these high-frequency memory devices is reliable data transfer. Specifically, when a data bit is to be read out of a memory device, for example, the data bit must be sampled by the memory controller while that data bit is valid. In other words, the clock delay between the data clock signal and the internal clock signal of the memory controller must be carefully selected to insure data sampling occurs during the data valid window.
One method known in the art for insuring reliable data transfer to and from a memory device is to provide a guaranteed setup and hold time. During a read operation, for example, guaranteed setup and hold comprises insuring a data bit is held or made available for a finite time window after the time at which the data bit has been latched out of the memory array to the output buffer to insure the data bit is available when sampling by the memory controller occurs—i.e., the “setup time”—and also providing a finite time window after the time at which the data bit was latched out of the memory array during which sampling of the data bit by the memory controller must occur to insure the data bit is sampled before another data bit is latched to the output buffer—i.e., the “hold time.” Thus, the guaranteed setup and hold method insures, at least for lower clock rates, that data is sampled during its data valid window. However, for high-frequency memory applications, providing a guaranteed setup time and hold time becomes impractical.
Another method known in the art for providing reliable data transfer to and from a memory device is to calibrate a memory device or a plurality of memory devices, a process commonly referred to as “read/write timing calibration.” One conventional method of calibrating a memory device is to construct a plurality of dedicated registers on each input/output line, or DQ line, of a memory device. A known, unique data pattern is written into the dedicated registers at a slow rate to insure reliable data transfer. The unique data pattern is then read out of the dedicated registers at a fast rate and the unique data pattern is compared to the known data pattern to see if any error occurred. If no error has occurred, the speed at which data is read out is increased and, if an error is detected, the speed at which data is read out is decreased. Calibration is continued until an optimum data transfer rate is determined. Although the above-described calibration method may be suitable for determining optimum data transfer rates at high-frequency, the addition of a plurality of dedicated registers to each DQ line of a memory device consumes surface area on a memory device and, thus, places a high “real estate cost” on the memory device. Further, the unique data pattern is limited in length by the number of dedicated registers available.
Accordingly, there is a need in the art for a method of performing read/write timing calibration and determining optimum data transfer rates for high-speed memory applications and, specifically, there is a need for such a method of performing read/write timing calibration that does not require dedicated calibration registers or other components and, hence, that does not consume valuable “real estate” on the surface of a memory device.
SUMMARY OF THE INVENTION
The present invention encompasses a number of embodiments of memory devices and methods of performing read/write timing calibration of these memory devices using a row or a redundant row. Use of a nonutilized row or redundant row for read/write timing calibration according to the present invention enables calibration to be performed during operation of a memory device without compromising data integrity. Further advantages include reliable calibration, minimal or nonexistent “real estate costs,” and simplicity resulting from the by-passing of address decoding.
In one embodiment of the present invention, a calibration fuse bank is provided on a memory device and the calibration fuse bank is programmed with the redundant rows not being utilized by the memory device for repair of its memory array. During read/write timing calibration, the calibration fuse bank is used to address a nonutilized redundant row of the memory array, and a unique data pattern can be written into and read out from this redundant row during calibration. In a further embodiment, the calibration fuse bank addresses a row or a nonutilized row of the memory array to be used for calibration.
In another embodiment of the present invention, the fuse bank of a memory device is used to identify and address a redundant row of the memory device not being utilized for repair of its memory array. Nonutilized redundant rows are identified by looking for fuses within the fuse bank that have not been blown (i.e., not programmed with a redundant row used for repair). During read/wr

Affiliated with

Also associated with

Rating

Read/write timing calibration of a memory array using a row... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Read/write timing calibration of a memory array using a row..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read/write timing calibration of a memory array using a row... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3213755