Read-write switching method for a memory controller

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules

Reexamination Certificate

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C711S157000, C711S167000, C711S169000

Reexamination Certificate

active

07093059

ABSTRACT:
A system includes a memory device. The memory device has a first bank and a second bank. A memory controller has a write request queue to store write requests. When a read bank conflict exists between a first read request to the first bank and a second read request to the first bank, a first write request is executed to the second bank during a delay. The delay takes place after the first read request is executed and before the second read request is executed.

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PCT International Search Report, Aug. 24, 2004 based on International Application No. PCT/US 03/39155.
PCT Search Report for corresponding PCT application performed by European Patent Office dated Aug. 24, 2004.

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