Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Utility Patent
1997-07-08
2001-01-02
Myers, Paul R. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S074000, C711S112000, C711S004000
Utility Patent
active
06170031
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to digital data storage systems and more particularly to an AT interface architecture employing state machines for use in a digital data storage system.
The use of state machines in the AT interface architecture of digital storage systems, and particularly of a flash solid state memory system has been described in U.S. Pat. No. 5,465,338, which patent is hereby incorporated by reference.
As described therein, a microcontroller controls the operation of a typical digital storage system. One function of the microcontroller is to transfer data between the host computer and buffer memory in response to read and write commands from the host computer. This transfer is automated by the inclusion of state machines in the AT interface. Four state machines are typically provided. A read state machine controls all aspects of READ commands, eliminating host related microcontroller activity during READ commands. A WRITE state machine controls all aspects of WRITE commands, eliminating host related microcontroller activity during WRITE commands. An UPDATE TASK FILE state machine is provided keep track of the data address and the number of sectors transferred upon request from either the WRITE or the READ state machine. Finally, a BYTE COUNT state machine controls the transfer of a sector of data between the host and the buffer.
As described, the four state machines eliminate microcontroller activity during READ and WRITE operations. However, the state machines do not provide for auto-writes on DMA commands, nor allow DMA commands to be blocked (multiple) commands. Furthermore, the state machines require a fixed amount of time between the transfer of sectors. This time requirement limits how fast the state machines can transfer multiple sectors. Consequently, the state machines, as described, cannot transfer data at the speeds desired by today's fast host computers. Finally, the microcontroller is only allowed to intervene at the start of a data transfer.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide an AT interface architecture comprised of state machines which provide for auto-writes of DMA commands, allow DMA commands to be blocked (multiple) commands, and allow the microprocessor to intervene between transfers of sectors in a block.
Another object of the invention is to provide a READ state machine which requires only one state time between sectors, and only seven state times between blocks.
Another object of the invention is to provide a WRITE state machine which requires only one state time between sectors, and only five state times between blocks.
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Flehr Hohbach Test Albritton & Herbert LLP
Myers Paul R.
Seagate Technology LLC
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