Read/write random access memory with data prefetch

Details Read/write random access memory with data prefetch Read/write random access memory with data prefetch

1989-08-09

1990-10-30

Popek, Joseph A.

Static information storage and retrieval

Addressing

Multiple port access

36523002, 36518904, G11C 700

Patent

active

049673980

ABSTRACT:
A dual port, random access, read/write memory is provided such that each microprocessor can access shared memory locations without regard to the state of the other microprocessor. Previously known dual port systems use delays, called wait states, or handshaking techniques to control memory acces and to resolve overlapping memory access requests. This invention avoids the need for special timing controls by improving memory response time. Once a valid address is placed on the address bus by the microprocessor, which is recognized by the memory as being within its range of assigned address values, the memory prefetches the data at that address may soon follow. If it does, then the data is placed on the data bus. If it does not, then the prefeteched data is ignored and a write operation takes place for the particular address.

REFERENCES:
patent: 4541076 (1985-09-01), Bowers et al.
patent: 4610004 (1986-09-01), Moller et al.
patent: 4616310 (1986-10-01), Dill et al.
patent: 4623990 (1986-11-01), Allen et al.
patent: 4627030 (1986-12-01), Barber
patent: 4660177 (1987-04-01), O'Connor et al.
N. Siddique et al., "Metastable-Free Arbitrator Coordinates Processors", Electronic Design, Apr. 14, 1988, pp. 107-112.

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