Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-11-01
2003-03-25
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S711000, C714S723000, C714S704000
Reexamination Certificate
active
06539506
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to devices and methods for testing read/write memories with integrated redundancy in which test patterns are written to a memory array and subsequently read out and compared and, if possible, until no more defects are present, as long as word lines and column select lines are replaced by redundant lines.
On one hand, to date, self-test architectures integrated on a memory chip have only tested whether or not the associated chip is free from defects. On the other hand, a redundancy analysis in which the lines to be replaced are determined from defect addresses has been carried out to date with the aid of an external computer, since it has been the case heretofore that firstly all of the defective memory cells have been determined and only then has a corresponding replacement strategy been determined. Since a test method of that type requires inter alia a very large defect storage device, that method can only be expediently implemented with an external computer and, in practice, cannot be implemented as a built-in self-test.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a read/write memory with an integrated self-test device and an associated test method, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and in which a complete self-test including redundancy analysis can be implemented without any significant external assistance.
With the foregoing and other objects in view there is provided, in accordance with the invention, a read/write memory, comprising at least one memory array having word lines and column select lines; and a self-test device monolithically integrated together with the at least one memory array, the self-test device having defect counters for the word lines and column select lines, redundancy consumption counters, stack storage devices for the word lines and column select lines to be repaired, a comparator connected to the stack storage devices for the word lines and column select lines to be repaired, a comparator connected to the defect counters for the word lines and column select lines, and a control unit.
In accordance with another feature of the invention, the control unit is programmed to perform the following functions in the following order:
a) initially setting all of the defect counters and redundancy consumption counters to zero;
b) comparing an information item written to the at least one memory array and an information item read from the at least one memory array and ascertaining a defective cell, with the comparators;
c) checking the word line and column select line associated with the defective cell to determine if it is already stored in the stack storage devices, and incrementing the counter associated with the respective word line and respective column select line only when one of the word line and the column select line has not yet been stored;
d) storing at least one of the word line and the column select line in the stack storage devices and incrementing the associated redundancy consumption counters if the associated defect counters exceed a repair threshold;
e) carrying out steps b) to d) for all prescribed test patterns and all cells of the at least one memory array or until one of the redundancy consumption counters overflows;
f) setting all of the defect counters to zero;
g) carrying out step b);
h) carrying out step c);
i) separately determining the word line and the column select line with the largest number of defects, with the comparators and the defect counters;
j) selecting one of the word line and the column select line with the largest number of defects;
k) storing the selected one of the lines with the largest number of defects in the stack storage devices and incrementing the associated redundancy consumption counter if the associated redundancy consumption counter has not yet overflowed;
l) carrying out step k) with the other of the lines selected according to step i) if the associated redundancy consumption counter has overflowed for the line selected according to step j);
m) terminating a test if the redundancy consumption counter overflows;
n) repeating steps f) to m) for all of the prescribed test patterns and for all of the memory cells of the at least one memory array; and
o) repeating step n) until all of the defect counters remain equal to zero or one of the redundancy consumption counters overflows.
In accordance with a further feature of the invention, there are provided fewer of the defect counters than the word lines and column select lines; an additional storage device for a maximum and an associated number of defects; and switches for assigning the defect counters to different groups of the word lines and column select lines; the control unit and the comparators determining and storing the word lines and column select lines with the largest number of defects within a group in the stack storage device instead of the word lines and column select lines with a previously largest number of defects, if the number of defects is greater than the previous largest number of defects, only the cells associated with the respective group of the word lines and column select lines being tested instead of all of the cells, and the test being repeated for all of the groups in the at least one memory array.
In accordance with an added feature of the invention, step j) is carried out by selecting one of the two lines having the largest number of defects.
In accordance with an additional feature of the invention, the defect counters have a different word width only for one word line and one column select line; the stack storage devices include a stack storage device for single-bit defects and a defect stack storage device; and the control unit is programmed to perform the following functions in the following order:
a) initially setting the defect counters and redundancy consumption counters to be equal to zero;
b) using the comparators for comparing information items written to and information items read out from the at least one memory array and ascertaining and storing a defective cell in the defect stack storage device;
c) checking the word line associated with the defective cell and the column select line with one of the comparators to determine if it is already stored in the stack storage device as a defective word line, as a defective column select line or as a single-bit defect, and skipping steps d) and e) if at least one of the word line and the column select line or the individual defect is already stored;
d) separately checking the word lines and column select lines associated with the defective memory cell and stored in the defect stack storage device for further defects and incrementing at least one of the defect counter associated with the word line and the defect counter associated with the column select line only when a respective further defect has not yet been stored in the stack storage device;
e) storing at least one of the word lines and the column select lines in the corresponding stack storage device and incrementing the associated redundancy consumption counter if the associated defect counter exceeds a repair threshold;
f) setting all of the defect counters to be equal to zero and repeating steps b) to e) for all test patterns and all memory cells of the at least one memory array; and
g) decreasing the repair threshold with one of the defect counters having a smaller word width and repeating step f) until, at a lowest repair threshold, the defect counters for all of the test patterns and all of the memory cells remain equal to zero or the redundancy counter overflows.
In accordance with yet another feature of the invention, in step d), further defects in the word line are sought only in the stack storage device for the column select lines to be repaired and further defects in the associated column select line are sought only in the stack storage device for the word lines.
In accordance with yet a further feature of the inventi
Lammers Stefan
Weber Werner
Greenberg Laurence A.
Mayback Gregory L.
Siemens Aktiengesellschaft
Stemer Werner H.
Tu Christine T.
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