Static information storage and retrieval – Plural shift register memory devices
Reexamination Certificate
2001-01-09
2002-08-20
Elms, Richard (Department: 2824)
Static information storage and retrieval
Plural shift register memory devices
C365S189120, C365S220000, C365S221000
Reexamination Certificate
active
06438017
ABSTRACT:
BACKGROUND
Devices such as the PA-8500 processor chip have a built-in self-test (BIST) engine which is programmed by a serial interface with staging registers. A staging register is conventionally used to handle the task of reading or writing a register through a serial interface. In particular, a staging register can transfer programming instructions that are written to a BIST engine and can in addition transfer self-test data for interpretation and analysis. When writing, a staging register collects serial data until a complete word has shifted in, and then transfers that word in parallel to a target register. When reading, a word of data is transferred in parallel to the staging register and is then shifted out serially. This method performs acceptably when target and staging registers have matching widths such as those used with the PA-8500, but is inefficient for mismatched target and staging register widths.
Accordingly, it would be advantageous to develop a system and method of efficiently programming a BIST engine incorporating narrow target registers. Additionally, it would be advantageous to develop such a method and system having simplified circuitry and operation. Moreover, it would be advantageous to develop such a system and method utilizing existing hardware and BIST register methodology to the greatest extent feasible.
SUMMARY OF THE INVENTION
The present invention is directed to a system and method that interface to the existing BIST register methodology and which employ a staging register to write to and read from a memory device having narrow memory registers.
Staging registers incorporate existing technology, but interfacing interleaved data in a wide staging register with a narrow register file, for example an eight-slot content addressable memory (CAM) with 10-bit slot width, in accordance with the present invention, provides new two-fold advantages. First, all the CAM slots can be loaded in a single shift operation instead of eight individual operations which would otherwise have been required. Second, the circuitry required is simplified by interleaving the data bits, such that reads and writes occur in eight consecutive clock periods. This system and method handle a stream of data as it is shifting within a staging register and transfer it to the CAM slots at the appropriate time.
In writing to a CAM or other target memory device having M memory registers, e.g., CAM slots, each with a width of X bits, M parallel datastreams are interleaved using conventional hardware or software techniques into a serial bitstream, which is then shifted into a staging register of N memory elements, such that typically N is greater than the product of X and M. The bits are interleaved within the bitstream so that all of the bit zeros of the interleaved datastreams shift in first, followed by all of the bit ones, the bit twos, . . . , and finally the bit (X−1)s. The bits are aligned so that all X value bits of the Mth parallel datastream occupy uniformly spaced non-adjacent memory elements that are interconnected with the input port of the target memory device. Concurrently the Mth memory register of the memory device is addressed, simultaneously writing all X bits to the Mth slot or register of the memory device. This simultaneous parallel writing operation occurs within a single clock period of the system. The bitstream is then shifted by one memory element, such that the bits of the (X−1) th parallel datastream now occupy the memory element locations interconnected with the memory device, the memory device address is decremented, and X bits are simultaneously written to the (X−1) th register of the memory device. This process is iterated until all M registers have been written within a total elapsed time of M clock periods.
Reading data from the memory device is performed in essentially a reverse process, incorporating interatively decrementing the memory register address, parallel reading all of the contents of the memory register into non-adjacent memory elements of the staging register, and shifting the bitstream in the staging register to interleave the bits from the next read cycle. As with writing, reading of all M registers occurs within an elapsed time of M clock periods. After reading, the interleaved bitstream is shifted out of the staging register and is de-interleaved using conventional hardware or software techniques.
The principles of the invention can be applied to a variety of configurations, including various bit widths and numbers of CAM slots, for example 16 CAM slots each 6 bits wide. Alternatively, the CAM can be replaced for example by a register file, a small segment of a larger memory, or a collection of narrow registers that communicate with a wide staging register.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention.
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