Read-write control for ECL memory

Details Read-write control for ECL memory Read-write control for ECL memory

1986-09-12

1988-08-02

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

For complementary information

365189, G11C 700

Patent

active

047617667

ABSTRACT:
In an ECL memory array, each bit cell has a neutral state prior to each writing of data into a cell following a read access. A write-read control is provided, having a data input, two outputs for supplying output control signals to write-read transistors and two control inputs for two independent write-read control signals. The two output control signals assuming an upper value, a lower value or a intermediate value in accordance with said two write-read control signals and the data input signal, whereby in a transition from a read access to a write access, the level change of the second write-read control signal changes from high to low prior to the change of the first write-read control signal from low to high, so that said write-read control signals are both high immediately prior to each write access.

REFERENCES:
patent: 3529294 (1970-09-01), Zuk
patent: 4272811 (1981-06-01), Wong
patent: 4398268 (1983-08-01), Toyoda
Patent Abstracts of Japan, vol. 1, No. 18, Mar. 1977, p. 385 E 76, Patent Publication No. 51-114834.
Patent Abstracts of Japan, vol. 6, No. 22, Feb. 9, 1982, p. 85 P 1651, Patent Publication No. 56-143594.

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