Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Patent
1992-10-30
1994-08-09
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
36518901, G11C 700
Patent
active
053372760
ABSTRACT:
A first threshold value for detecting a potential indicating a read state, and a second threshold value for detecting a write state are set in an inverter circuit, to which a read/write signal R/W for setting the state of a memory cell is supplied, by means of a P-channel transistor, an N-channel transistor, and another P-channel transistor which is much smaller in gate width than the above transistors. The first or second threshold value is selected by a logic circuit constituted by an inverter circuit and a delay circuit in accordance with the level of the read/write signal R/W. Therefore, a change from a read state to a write state and a reverse change can be detected at high speed, thus providing a read/write control circuit for a random access memory, which can increase the speed of a read operation immediately after a write operation while ensuring a sufficient data write time, and can shorten the write recovery time.
REFERENCES:
patent: 4811292 (1989-03-01), Watanabe
patent: 4841488 (1989-06-01), Sanada
patent: 4894803 (1990-01-01), Aizaki
patent: 4972375 (1990-11-01), Ueno
patent: 5031149 (1991-07-01), Matsumoto
Kabushiki Kaisha Toshiba
LaRoche Eugene R.
Zarabian A.
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