Read-write circuit for short bit line DRAM

Details Read-write circuit for short bit line DRAM Read-write circuit for short bit line DRAM

2009-04-02

2009-12-15

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S189150, C365S189160, C365S189170, C365S194000, C365S207000

Reexamination Certificate

active

07633791

ABSTRACT:
A read-write circuit serving as a global sense amp for SBL (short bit line) DRAM is realized, wherein the read-write circuit includes a common line, such that the common line is used for connecting a read circuit, a latch circuit, a write circuit, a left select circuit and a right select circuit in the global sense amp for transferring write data to memory cells through a local sense amp and reading a stored data from the memory cells through the local sense amp. In doing so, the common line is useful for realizing a layout more effectively within a limited pitch, and also reducing area of the layout. And the read-write circuit is efficiently connected to a local sense amp in the short bit line memory architecture for reading and writing data. In addition, alternative circuits are described for implementing the read-write circuit for the short bit line DRAM.

REFERENCES:
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patent: 6426905 (2002-07-01), Dennard et al.
patent: 6456521 (2002-09-01), Hsu et al.
patent: 2003/0103368 (2003-06-01), Arimoto et al.
A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM in VLSI Circuits, Digest of Technical Papers, May 1993.
A 322 MHz Random-Cycle Embedded DRAM With High-Accuracy Sensing and Tuning, IEEE Journal of Solid-State Circuits, vol. 40, No. 11, Nov. 2005.
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier, IEEE International Solid-State Circuits Conference, pp. 486, 2007.

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