Read/write architecture for MRAM

Details Read/write architecture for MRAM Read/write architecture for MRAM

2001-07-13

2002-07-23

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S171000, C365S173000

Reexamination Certificate

active

06424562

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a read/write architecture for a magnetoresistive random access memory (MRAM) addressable via word lines and bit lines. The MRAM has a multiplicity of ferromagnetic memory elements that are disposed at crossovers between word lines and bit lines. The memory elements at the crossovers form rows and columns of a matrix, which furthermore each contain two ferromagnetic layers separated by a separating layer, and whose resistance perpendicular to the layer sequence is in each case higher than that of the word lines and of the bit lines and depends on the magnetization state of the ferromagnetic layers.
As is known, MRAMS are non-volatile random access memories which, in comparison with other types of non-volatile and also volatile memories such as, for example, DRAMs, FRAMS (ferroelectric RAMs), EEPROMS (electrically erasable and programmable ROMs or read-only memories) and FLASH memories, are distinguished by advantages such as, in particular, high storage densities ranging into the order of magnitude of 100 Gbits/chip or more, simple process architectures and hence low fabrication costs per bit.
The cell arrays of MRAMS expediently contain metallic word lines and bit lines, also called write lines and read lines, which are disposed in a matrix-like manner and are disposed one above the other such that they respectively run in the x-direction and y-direction in a Cartesian xy coordinate system, and between which the ferromagnetic memory elements are provided at the crossovers between the word lines and the bit lines. The ferromagnetic memory elements contain at least two ferromagnetic layers that lie one above the other and are magnetically decoupled, which is effected by a separating layer provided between the ferromagnetic layers. The separating layer may be a tunneling barrier made, for example, of aluminum oxide (Al
2
O
3
) or a non-ferromagnetic conductive layer made, for example, of copper.
The ferromagnetic layers are composed, for example, of iron, cobalt, nickel, permalloy (NiFe), etc., it being possible for them to contain additions such as platinum, for example, which promote a finely crystalline state.
The ferromagnetic layers may have a layer thickness of between 3 and 20 nm, while the separating layer located between them may have a thickness of 1 to 3 nm.
The ferromagnetic layers of each memory element have switching fields of different magnitude and can therefore be subjected to magnetization reversal independently of one another by switching currents in the word lines and bit lines, which form interconnects. In this case, the resistors of the individual memory elements have resistances dependent on the relative magnetization of the ferromagnetic layers that form them. If both ferromagnetic layers are magnetized parallel to one another, then the memory element has a resistance R
0
, while a resistance R
0
+&Dgr;R (&Dgr;R>0) is present in the case of antiparallel magnetization of the two ferromagnetic layers. The ratio &Dgr;R/R
0
is about 0.1 . . . 0.2. This effect is referred to as the magnetoresistance effect. The term magnetoresistive memory elements is also customary for the ferromagnetic memory elements.
These two resistances of the ferromagnetic layers, that is to say the resistance R
0
for parallel magnetization and the resistance R
0
+&Dgr;R for the antiparallel magnetization, can be assigned the quantities “0” and “1” of binary memories.
Writing to MRAMs is simple, in principle, if the fact that the requisite switching field strengths have to be achieved by the interconnects is disregarded. It has proved more difficult for the information stored as resistances in the memory elements to be read out reliably and as simply as possible, that is to say without the assistance of selection transistors, which enlarge the memory cell areas and make the fabrication process more complex.
Various efforts have already been made to configure the read-out securely and reliably without selection transistors. A principal problem in reading the memory cells disposed in high memory density with a cell area of 4 F
2
(F=minimum feature size) is that each memory cell, that is say each resistive element whose resistance is to be determined, is “shunted” through a multiplicity of parallel current paths, which makes it problematic to determine the resistance exactly, especially in large memory cell arrays.
In order to overcome these difficulties, two read-out methods have previously been disclosed for MRAMS.
In the first method, the word lines and the bit lines are electrically insulated from one another, and the read current flows through a relatively small number, for example ten, of memory elements connected in series. The resistance of a relevant memory element can then be inferred from the change in the read current by a relatively complex circuit (in this respect, see the reference by D. D. Tang, P. K. Wang, V. S. Speriosu, S. Le, R. E. Fontana, S. Rishton, IEDM 95-997).
The method requires write currents through the two interconnects (word line and bit line) which cross at the relevant memory element. The number of memory elements connected in series is limited by the relative change in the total resistance, which change becomes ever smaller as the number increases, and the measurement of the current change, which measurement becomes more difficult. The small number of memory elements that can be connected in series with one another necessitates a large outlay on circuitry for the periphery of the memory array and thus results in a large area requirement for the read electronics.
The second read-out method consists in all word lines and bit lines, with the exception of the word line connected to the selected memory cell, being put at “0” potential. A potential not equal to zero is applied to the selected word line, while the selected bit line and all other bit lines are brought to a “virtual” zero potential by using an operational amplifier for current measurement (in this respect, see Published, Non-Prosecuted German Patent Application DE 197 40 942 A1).
Both methods have the disadvantage that they are based on the determination of the absolute value of the resistance of the individual memory elements, as a result of which very stringent technological requirements are placed on accurate, reproducible and homogeneous setting of the resistances over the entire memory cell array and also over a semiconductor wafer or a plurality of semiconductor wafers. Equally, it must be taken into consideration here that in the case of the relatively small changes of &Dgr;R/R
0
, temperature fluctuations can bring about changes in the resistance which make it more difficult to reliably determine the magnetization states of individual memory elements and hence to read the latter. In addition, in the second method, the finite bit line resistances have the effect that the condition of a virtual zero potential is met only at the ends of the bit lines, with the result that parasitic shunt currents have an adverse effect in the case of long bit lines.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a read/write architecture for a MRAM that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which, in conjunction with a simple construction, allows reliable reading of the memory cell array and does not place unrealistically stringent requirements on the exact, reproducible and homogeneous setting of the resistances of the individual memory cells.
With the foregoing and other objects in view there is provided, in accordance with the invention, a read/write architecture for a magnetoresistive random access memory (MRAM). The read/write architecture contains bit lines, word lines crossing over the bit lines, and a multiplicity of ferromagnetic memory elements disposed at the crossover points of the word lines and the bit lines and forming rows and columns of a matrix. Each of the ferromagnetic memory elements contains a l

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