Read/write amplifier for a DRAM memory cell, and DRAM memory

Details Read/write amplifier for a DRAM memory cell, and DRAM memory Read/write amplifier for a DRAM memory cell, and DRAM memory

2001-10-30

2004-07-27

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S205000, C365S207000

Reexamination Certificate

active

06768686

ABSTRACT:

The present invention relates firstly to a read/write amplifier for a DRAM memory cell in accordance with claim
1
. Furthermore, the invention relates to a DRAM memory in accordance with claim
10
. Finally, the invention also relates to a method for evaluating DRAM memory cells of a DRAM memory.
DRAM memory cells (Dynamic Random Access Memory cells) and memories represent an important type of memory for storing digital information. A DRAM is a memory in which, after specification of an address, data can be stored and read out again under this address. In DRAM memory cells and memories, respectively, the information is not stored as a switching state of a circuit but rather as a quantity of charge on a capacitance. Consequently, such a memory cell can be formed with only a storage capacitor and a selection transistor. Since every capacitor has leakage currents and leakage currents also flow via the selection transistor, the information in the DRAM memory cell is continuously degraded. The information content of the memory cell is therefore lost over time. In order to avoid this, the contents of the memory cells are periodically read out, the memory contents are evaluated and the memory cell is written to anew. This means that the charge contents of the storage capacitors are refreshed again, which is referred to as “refresh”.
DRAM memory cells are usually interconnected to form memory cell arrays, a DRAM memory having one or a plurality of such memory cell arrays. Each memory cell is connected, or wired, to the cell periphery via at least one word line and a bit line, the word line(s) and the bit line being routed via the memory cell and being oriented at least substantially perpendicularly to one another. Through activation of a specific word line, all the memory cells connected thereto can, via their bit lines, be read, written to or refreshed with regard to their information content.
In DRAM memory cells, digital information items can be stored for example in the form of logic “0” and “1”. Each of these logic information items is assigned a specific voltage value. By way of example, the voltage value for logic “0” may be zero volts, while the voltage value for logic “1” is 2 volts, for example. Before the memory cells are read, a reference voltage, for example a voltage of 1 volt is applied to all the bit lines. During the reading of the memory cell, the voltage value will either increase somewhat or else decrease, depending on the information content of the memory cell. This voltage change is compared with a reference voltage prevailing on a reference bit line. In this case, the reference bit line is connected to a memory cell which is currently not being evaluated. If the voltage value on the bit line that is to be evaluated is higher than the reference voltage, the information content logic “1” had been written to the memory cell. In the case of smaller voltage values, the information logic “0” had been written to the memory cell. The voltage signal read from the bit line to be evaluated and the reference bit line is conditioned and processed further, for example amplified, in a read/write amplifier.
Depending on the memory architecture, the bit lines (BL) of the memory cells to be evaluated and the respective reference bit lines (BBL) may be arranged beside one another in one and the same memory cell array and thus form a bit line pair in each case. In other memory architectures, the reference bit lines are each situated in a different memory cell array.
As has already been mentioned, the logic information items “0” and “1” are stored in the form of charge in cell capacitances in the case of a DRAM memory. These charges are converted into a small voltage signal in a first section of the evaluation. The read/write amplifier circuit of a DRAM memory has the task of amplifying this voltage signal to a full level. The amplified signal serves, on the one hand, for writing back the information that was destroyed in the memory cell during read-out, and, on the other hand, for forwarding the information read to the DRAM periphery. The read/write amplifier circuit must perform the aforementioned tasks with high evaluation reliability and speed in conjunction with the smallest possible space requirement.
Conventional read/write amplifier circuits generally comprise a number of components for assessing, amplifying and forwarding voltage signals read from the bit lines and reference bit lines.
These components include, for example, at least one “N latch circuit” (NL), which serves for producing the low level for the voltage value. The N latch circuit has the task of amplifying a voltage signal to this low level. With reference to the numerical example mentioned further above the low level might be, for example, the “0” volts value.
Furthermore, the read/write amplifier may have at least one “P latch circuit” (PL), which serves for producing a high level. Thus, the P latch circuit serves for amplifying a voltage signal to this high level, which corresponds to the “2” volts value, for example, in connection with the numerical example mentioned above.
A further component for the read/write amplifier is, for example, the “equalizer” (EQ), which serves for producing a reference voltage value (precharge level) on the bit lines.
Furthermore, the read/write amplifier may have at least one “bit switch” (BS), which is used for connecting a bit line pair—selected for example by a “column address”—to external data lines.
Finally, the read/write amplifier may have one or more transistors for changing over between different bit lines. Such transistors are, for example, selection transistors (MUX) for multiplexing the read/write amplifiers between different bit line pairs.
The individual components of the read/write amplifier will be explained in more detail in the further course of the description.
FIG. 1
diagrammatically illustrates a DRAM memory which is known from the prior art and in which different read/write amplifier circuits (SA) are utilized for bit line pairs of adjacent memory cell arrays (Arrays). Such read/write amplifier circuits are also referred to as “shared sense amplifier”. An arrangement of the different read/write amplifier circuits as illustrated in
FIG. 1
already leads to a favorable ratio of the area proportions of memory cells and read/write amplifier circuits.
Depending on the DRAM memory type, the area required by the read/write amplifier circuit(s) can vary greatly in relation to the total area of the memory. The absolute area of a read/write amplifier circuit usually remains the same, so that the relative size of the read/write amplifier circuit in the overall memory changes depending on the memory architecture. In this case, the relative size of the read/write amplifier circuits in a DRAM memory may be between 5% and 30% of the total memory area. There is, therefore, a need to minimize the required area of the read/write amplifier circuits as well as possible.
In a known DRAM memory, with the aid of a second metal plane in the integrated circuit per memory cell array, it is possible to evaluate an additional bit line pair with each read/write amplifier circuit. This architecture thus halves the required number of read/write amplifier circuits in comparison with a conventional memory architecture as described above. However, the use of two metal planes is very cost-intensive and hence disadvantageous.
Another approach which is known from the prior art and serves for saving read/write amplifier area consists in the multiple use of the same read/write amplifier for different bit line pairs by multiplexing. Such an approach is illustrated for example in FIG.
2
and is explained in more detail in the context of the description of the figures. This known principle is based on the multiple utilization of read/write amplifier circuits for bit line pairs in the same memory cell array. The read/write amplifier (SA) is connected by selection transistors (MUX) to respectively complementary halves of bit line pairs of a cell array. The connected bit line pairs can be evalu

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