Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-01-05
2001-07-10
Rinehart, Mark H. (Department: 2756)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S155000, C711S171000, C365S230030, C365S185110
Reexamination Certificate
active
06260103
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to memory devices and more particularly to the configuration and use of sense amplifiers for memories in which read and write operations can be performed simultaneously.
BACKGROUND OF THE INVENTION
There are many different types of memory devices available today with a wide range of capabilities and operating characteristics. As with many other types of integrated circuit devices, there is a focus on increasing memory device performance, speed, and utility while reducing or maintaining power consumption at a low level.
Flash memory, an increasingly popular type of memory, is a nonvolatile memory that is electrically erasable and electrically programmable. In many cases, flash memories are now being used for functions traditionally provided by Electrically Erasable Programmable Read Only Memories (EEPROMS) and Static Random Access Memories (SRAMs). Such applications include Basic Input/Output System (BIOS) memories, for example. Other applications for flash memory include cellular telephones, other personal computer memories, automotive and airplane control, handheld communications devices, and digital cameras.
Further, flash memory can be used to store both code and data. In a cellular phone application, for example, a flash memory can be used to store factory data, operating routines, user data, and system and network data.
In a flash memory, as in other types of memories, there are three basic types of memory access operations: a program (also referred to as write) operation, an erase operation, and a read operation.
In currently available flash memories, each of the different memory operations requires a different amount of time to perform. For example, in some current flash memories, a read operation may take approximately 100 nanoseconds to perform, while a program operation may require about 10 microseconds and an erase cycle may take as long as one second to perform.
The difference between the time required for erase and program cycles and the time required for a read cycle is significant. Therefore, it is useful to be able to perform read operations concurrently with performing either program or erase operations. In this manner, read operations do not have to be stalled while waiting for program or erase operations to complete and program or erase operations do not have to be suspended in order that speed critical read commands can be serviced.
A flash memory or other memory that is capable of performing read operations while program and/or erase cycles are being performed in the background is referred to as a “read-while-write” (RWW) memory. A RWW memory provides increased efficiency and speed, along with other advantages.
For example, in some prior systems, multiple memories are provided such that read and write or program operations can be performed concurrently. With the use of memories that include RWW capability, it may be possible to achieve the same system performance using only one memory. RWW memories also facilitate increasingly important multitasking capabilities.
In order to be able to perform read and program or erase cycles concurrently on a single flash memory device, some additional circuitry must be provided. For example, sense amplifiers, also referred to as sense amps, are used to detect the values stored in particular flash cells during a read operation. Typically, 8 or 16 flash memory cells are read at one time. The number of flash memory cells read at one time for a particular flash memory is referred to as the number of internal reads possible. To enable this parallel read operation, a same number of sense amplifiers as the number of flash memory cells to be read is provided. For example, if sixteen flash memory cells are to be read during a read operation, sixteen sense amplifiers are available for the read operation.
While sense amplifiers are not required for the actual programming or erasing operations, a verify step following each program or erase operation does use sense amplifiers. The verify operation is similar to a read operation and is used to verify the success of a program or erase operation.
Several flash memory cells are also often programmed and verified in parallel as described above in reference to the read operation. Typically, for a given flash memory, a verify operation reads the same number of memory cells in parallel as are read during a read operation. For this reason, some currently available RWW memories include and use twice the number of sense amplifiers as the number of flash memory cells that are read during a read operation such that read and verify operations can be performed simultaneously. In the example provided above in which a read operation to the flash memory array causes sixteen flash memory cells to be read at a time, such prior memories use 32 sense amplifiers in order to be able to perform read operations concurrently with program and/or erase operations.
A disadvantage associated with current RWW memories is that significant additional space on the integrated circuit is required to implement RWW functionality. Some of this additional space is due to the number of additional sense amplifiers required to be able to perform a read operation concurrently with a write and/or erase operation.
Another disadvantage associated with current RWW memories is that the additional sense amplifiers provided to perform the read and verify operations concurrently increase the peak power consumption of the memory as compared to similar memories without RWW capability.
The additional silicon space and power required to implement RWW functionality is a drawback in today's power electronics applications that are sensitive with respect to power, cost and space.
SUMMARY OF THE INVENTION
A read-while-write (RWW) memory device comprises a memory array including a read memory plane and a write memory plane. The RWW memory also includes a first number of read sense amplifiers to be coupled in parallel to the read memory plane in response to a memory read operation wherein the first number is greater than one. The RWW memory also includes a second number of verify sense amplifiers to be coupled to the write memory plane in response to one of a memory write or erase operation wherein the second number is greater than zero and less than the first number.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
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International Seach Report, PCT/US98/25217, 5 pages.
Alexis Ranjeet
Larsen Robert E.
Faatz Cynthia T.
Intel Corporation
Rinehart Mark H.
Willett Stephan
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