Read-while-write flash memory devices having local row...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185110, C365S230060, C365S189011

Reexamination Certificate

active

07079417

ABSTRACT:
A flash memory device can include a local row decoder circuit that is configured to drive word lines coupled to a bank of a flash memory responsive to separate read and write control signals provided thereto from outside the local row decoder circuit. Multiple local row decoder circuits can, therefore, be controlled by a single global row decoder circuit that provides the separate read and write control signals to each of the local row decoder circuits. By locating the combinatorial logic circuits used for decoding addresses in the global row decoder circuit, rather than in the local row decoder circuits, the local row decoder circuits may have reduced size, thereby allowing further reductions in the size of the flash memory device. For example, in some embodiments according to the invention, a NAND logic circuit used for address decoding is located in the global row decoder circuit, thereby allowing the area allocated to the local row decoder circuit to be reduced. Furthermore, because the may be many local row decoder circuits implemented in the flash memory device, the total size of the flash memory may be reduced.

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European Search Report for European Application No. 03 01 7907 mailed on Dec. 20, 2005.

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