Read resettable memory circuit

Details Read resettable memory circuit Read resettable memory circuit

1982-04-14

1984-07-10

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Flip-flop

307269, G11C 1100

Patent

active

044596839

ABSTRACT:
A read resettable memory circuit contains a flip-flop circuit (10) consisting of a flip-flop (FF) and an edge-triggered control circuit (CC) and a fall-through latch (16). The control circuit sets the flip-flop in response to a selected edge transition in a first clock (.0..sub.1) when an appropriate external logical set signal (S) is received and resets the flip-flop in response to a selected edge transition in a second clock (.0..sub.2) when an appropriate feedback logical reset signal (R) is received. The latch provides the reset signal at a value corresponding to the current logic state of the flip-flop during each period running from the selected edge transition of the second clock to its opposite edge transition and at a value corresponding to the logic state of the flip-flop that exists just before each opposite edge transition of the second clock during each remaining following period.

REFERENCES:
patent: 4224533 (1980-09-01), Lai
patent: 4379241 (1983-04-01), Pumo

Affiliated with

Also associated with

Rating

Read resettable memory circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Read resettable memory circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read resettable memory circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1579843