Read out scheme for several bits in a single MRAM soft layer

Details Read out scheme for several bits in a single MRAM soft layer Read out scheme for several bits in a single MRAM soft layer

2007-03-06

2007-03-06

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S173000, C365S209000, C257S295000

Reexamination Certificate

active

10925487

ABSTRACT:
A magnetic tunnel junction (MTJ) device is configured to store at least two bits of data in a single cell utilizing the variable resistance characteristic of a MTJ. The MTJ includes a soft and two fixed magnetic layers with fixed field directions oriented in perpendicular directions. The soft magnetic layer is separated from the fixed layers by insulating layers preferably with different thicknesses, or with different material compositions. The resulting junction resistance can exhibit at least four distinct resistance values dependent on the magnetic orientation of the free magnetic layer. The cell is configured using a pattern with four lobes to store two bits, and eight lobes to store three bits. The resulting cell can be used to provide a fast, non-volatile magnetic random access memory (MRAM) with high density and no need to rewrite stored data after they are read, or as a fast galvanic isolator.

REFERENCES:
patent: 6166539 (2000-12-01), Dahlberg et al.
patent: 6166948 (2000-12-01), Parkin et al.
patent: 6545906 (2003-04-01), Savtchenko et al.
patent: 6713195 (2004-03-01), Wang et al.
patent: 6812537 (2004-11-01), Okazawa et al.
patent: 6980469 (2005-12-01), Kent et al.
patent: 2004/0012994 (2004-01-01), Slaughter et al.
patent: 2004/0065906 (2004-04-01), Asao
patent: 2005/0259463 (2005-11-01), Lim
Horowitz, P., et al., “The Art of Electronics,” 2nd Edition, New York, Cambridge University Press (1989) pp. 88-91 and 255-257.
Tehrani, S., et al., “Recent Developments in Magnetic Tunnel Junction MRAM,” IEEE Transactions on Magnetics, vol. 36, No. 5. (Sep. 2000) pp. 2752-2757.
DeBrosse. J., et al., “A High-Speed 128-kb MRAM Core for Future Universal Memory Applications,” IEEE Journal of Solid-State Circuits, vol. 39, No. 4, (Apr. 2004) pp. 678-683.
Durlam, M., et al., “A 0.18 μm 4 Mbit Toggling MRAM,” 2004 IEEE International Conference on Integrated Circuit Design and Technology, (2004) pp. 27-30.

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