Read only memory with neighboring memory blocks sharing...

Details Read only memory with neighboring memory blocks sharing... Read only memory with neighboring memory blocks sharing...

1999-07-26

2001-06-26

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S051000, C365S063000

Reexamination Certificate

active

06252817

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a read only memory, and more particularly to a semiconductor read only memory in which a selected memory block shares its assigned block selection lines with its neighboring memory block.
BACKGROUND OF THE INVENTION
Mask ROMs with NOR-type memory cell arrays has been disclosed in Symposium on VLSI Circuit on August 1988, entitled 16 Mb ROM Design Using Bank Select Architecture, pp.85-88, in which bit lines are constructed in a hierarchical arrangement. In the technique of the article, the reading-out process is accomplished through three steps: (a) precharging main bit lines into predetermined voltage levels; (b) sensing a voltage level of a main bit line to determine whether a selected memory cell is an on-cell or an off-cell; and (c) outputting data detected from the selected memory cell to the output of the memory device. Each of the banks has bank selection transistors which connect memory cells to bit lines and ground lines.
In a typical architecture of the mask ROM, bank selection transistors are controlled by bank selection lines and ground selection lines. These are arranged between the memory banks, which take up space. It is desired to find arrangements that save space so that the memory can become more compact.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a read-only memory having an efficient architecture in selecting and activating memory banks. This is accomplished by having neighboring memory blocks share the block selection lines that are between them.
More specifically, a memory of this invention includes a plurality of memory blocks having a plurality of memory cells arranged in a matrix type. The memory cells are coupled to a plurality of wordlines. A plurality of selection lines is disposed between the memory blocks. The selection lines are divided into a plurality of groups, and each of the groups is shared by neighboring memory blocks. The memory includes means for selecting a corresponding one of the groups in response to address informing signals.
Other aspects of the present invention are a wordline switching circuit coupled between conductors carrying wordline drive signals and the wordlines and, a block selection line switching circuit coupled between the block selection line signals and the conductors block selection carrying lines. A switching control circuit supplies selection control signals to the wordline switching circuit and the block selection line circuit. The switching control circuit generates the selection control signals in response to address informing signals.
In a preferred feature of the invention, the wordline switching circuit, the block selection line switching circuit, the switching control circuit and the discharge circuit are provided in a decoding unit.
The invention preferably also includes discharge circuits. The selection lines are coupled to the discharge circuits, which pull down voltage levels of the selection lines that are not selected in response to the block selection control signal.
Since the block selection lines are shared, fewer are needed between the memory blocks. This and other features and advantages of the invention will be understood better in connection with the Detailed Description of the invention and drawings.


REFERENCES:
patent: 5245570 (1993-09-01), Fazio et al.
patent: 5706245 (1998-01-01), Kim
patent: 5825683 (1998-10-01), Chang
patent: 5943289 (1999-08-01), Ahn et al.
patent: 6034911 (2000-03-01), Aimoto et al.

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