Read-only memory for microprocessor systems having shared addres

Details Read-only memory for microprocessor systems having shared addres Read-only memory for microprocessor systems having shared addres

1988-09-15

1990-07-03

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Plural use of terminal

36523008, 36518905, G11C 800

Patent

active

049396927

ABSTRACT:
A read-only memory incorporated on a single substrate for use with a microprocessor system is described. The memory includes a transceiver for passing data and first address signals, and the transceiver has a first side for coupling to a first plurality of lines. A first latch for latching the first address signals is provided, wherein the first latch has a first side coupled to a second side of the transceiver. A first buffer is provided, the first buffer having a first side coupled to a second side of the first latch. A second buffer for buffering second address signals is provided, the second buffer having a first side for coupling to a second plurality of lines. A second latch for latching the second address signals is provided, wherein the second latch has a first side coupled to a second side of the second buffer. A third buffer is provided, and the third buffer has a first side coupled to a second side of the second latch. A memory array for storing the data is further provided. The read-only memory also includes an address decoder for decoding the first and second address signals for selecting data from the memory array, wherein th address decoder has (1) a first input coupled to a second side of the first buffr, (2) a second input coupled to a second side of the third buffer, and (3) an output coupled to the memory array. A fourth buffer for passing the data from the memory array to the transceiver is included. The fourth buffer has (1) an input coupled to an output of the memory array and (2) an output coupled to the second side of the transceiver. The read-only memory also includes an output buffer having (1) an input coupled to the second side of the first latch and (2) an output for providing latched address signals as an output from the read-only memory.

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