Read only memory device with high speed data output unit

Details Read only memory device with high speed data output unit Read only memory device with high speed data output unit

1991-03-12

1993-08-31

Pascal, Robert J.

Static information storage and retrieval

Read/write circuit

Differential sensing

365205, G11C 1134, G11C 700

Patent

active

052415058

ABSTRACT:
A read only memory device comprises a memory cell array, a selector unit interconnecting one of the memory cells to an input node of a sense amplifier unit for producing a read-out signal at a read-out node, a reference unit for producing a reference signal with an intermediate voltage level between voltage levels corresponding to logic "1" bit and logic "0" bit, and a voltage comparator coupled to the sense amplifier unit and the reference unit, wherein the sense amplifier unit has a load transistor continuously supplying current to the read-out node, a transfer gate transistor for interconnecting the input node and the read-out node under the control of an inverting amplifier coupled to the input node, and a charging transistor for providing an auxiliary current path to the read-out node upon rapid decay in voltage level at the read-out node, thereby causing the read-out signal to quickly become stable.

REFERENCES:
patent: 4459497 (1984-07-01), Kuo et al.
patent: 5142495 (1992-08-01), Canepa

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