Read only memory circuit

Details Read only memory circuit Read only memory circuit

1979-11-06

1981-05-26

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365189, 307DIG3, G11C 700, G11C 706

Patent

active

042701899

ABSTRACT:
The disclosure shows a read only storage (ROS) formed of a matrix of rows and columns of field effect transistor (FET) devices which is personalized by the presence or absence of a gate at the memory device location. All circuits on the chip are controlled and restored to initial conditions by a single train of clock pulses including the row and column addresses, the array select and the output sensing. In addition the output signal is communicated directly to the output line control device without withdrawing current to set the outputs latch thereby making the output truely delayless.

REFERENCES:
patent: 3846643 (1974-11-01), Chu et al.
patent: 4031524 (1977-06-01), Heeren
patent: 4053873 (1977-10-01), Freeman et al.
Wilson, "Cell Layout Boosts Speed of Low-Power 64-K Rom", Electronics, 3/30/78, pp. 96-99.
Itoh, et al., "A High-Speed 16K-Bit NMOSRAM", 1976 IEEE International Solid-State Circuits Conf., pp. 140-141, Digest of Tech. Papers.
Lee, "Cross-Coupled Latch for Memory Sensing", IBM Tech. Disc. Bul., vol. 17, No. 5, 10/74, pp. 1361-1362.

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