Read-only memory cell configuration with trench MOS transistor a

Details Read-only memory cell configuration with trench MOS transistor a Read-only memory cell configuration with trench MOS transistor a

1998-05-28

2000-03-28

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257330, 257332, 257391, H01L 2976

Patent

active

060435437

ABSTRACT:
A read-only memory cell configuration and a method for its production include a substrate formed of semiconductor material having memory cells disposed in a cell field in a region of a main area. Each memory cell has at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode. The drain region is connected to a bit line and the gate electrode is connected to a word line. The MOS transistor is formed by a trench starting at the main area and reaching as far as the source region. Side walls of the trench are disposed at an angle of approximately 45.degree. to approximately 80.degree. relative to the main area and are doped with a doping material of a predetermined conductivity for defining the programming of the MOS transistor.

REFERENCES:
patent: 4198693 (1980-04-01), Kuo
patent: 4263663 (1981-04-01), Powell
patent: 4296429 (1981-10-01), Schroeder
patent: 4503449 (1985-03-01), David et al.
patent: 4859615 (1989-08-01), Tsukamoto et al.
patent: 4929987 (1990-05-01), Einthoven
patent: 4954854 (1990-09-01), Dhong et al.
patent: 5057887 (1991-10-01), Yashiro et al.
patent: 5300804 (1994-04-01), Arai
Patent Abstracts of Japan No. 630 24 660 (Hiroyuki), dated Feb. 2, 1988.
Patent Abstracts of Japan No. 601 24 970 (Akio et al.), dated Jul. 4, 1985.

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