Read-only memory cell configuration with steep trenches

Details Read-only memory cell configuration with steep trenches Read-only memory cell configuration with steep trenches

1994-05-18

1995-09-26

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257330, 257402, 257623, H01L 2702, H01L 2710

Patent

active

054536375

ABSTRACT:
A semiconductor integrated circuit of a read-only memory device having steep trenches is disclosed. The memory device includes a substrate that has a plurality of interwoven chessboard-like trenches, each trench including opposing and sloping side walls. The memory device also includes a plurality of drain/source regions formed on the substrate. Neighboring drain/source regions are positioned, in conformity with the presence of mesas and bottoms of the trenches, in a high and low interwoven manner in a first direction along the plane of the substrate at an altitude relative to the plane of the substrate, thereby forming a generally vertical drain/source channel between each pair of neighboring drain/source regions. The memory device further includes a gate oxide layer formed on the substrate, and a plurality of gate regions formed on the surface of the gate oxide layer. Neighboring gate regions are positioned, in conformity with the presence of mesas and bottoms of the trenches, in a high and low interwoven manner in a second direction along the plane of the substrate at an altitude relative to the plane of the substrate, wherein the second direction is orthogonal to the first direction.

REFERENCES:
patent: 5119165 (1992-06-01), Ando
patent: 5185646 (1993-02-01), Mizuno
patent: 5300804 (1994-04-01), Arai
patent: 5306941 (1994-04-01), Yoshida

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