Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-30
2001-08-28
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S301000, C257S302000, C257S306000, C257S329000, C257S336000, C257S391000, C257S392000, C257S397000, C257S390000, C257S501000, C257S510000, C257S513000, C438S128000, C438S129000, C438S130000, C438S275000, C438S278000, C438S290000
Reexamination Certificate
active
06281557
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a read-only memory cell array and a method for producing the memory cell. In semiconductor technology, read-only memories (ROM) can be implemented by a memory cell array in which the individual memory cells essentially include vertical MOS transistors in a semiconductor substrate. When the memory cell configuration is read out, the individual memory cells are selected via a word line. The gate electrode of the MOS transistors is in each case connected to the word line. The input of each MOS transistor is connected to a reference line, and the output to a bit line. During the reading procedure, it is assessed whether or not a current is flowing through the transistor. The logic values zero and one are assigned as a function of this. Technically, the zero and one values are stored in the read-only memory by virtue of the fact that, in memory cells in which the logic value assigned results in “no current flow through the transistor”, neither a MOS transistor nor a connective connection to the bit line is produced. Alternatively, the two logic values can be implemented by MOS transistors which have different threshold voltages owing to different implantations in the channel area. Such memory cells are described in detail in German Patents DE 195 14 834 C1 and DE 44 37 581 C2, for example.
In the known fabricating methods, vertically disposed doped areas to be produced in the semiconductor substrate are used to form the vertical MOS transistors. Long trenches which extend in parallel are etched into the semiconductor substrate and are filled with an insulation material. Strip-shaped, doped regions which are oppositely doped to the semiconductor substrate form a bit line used to read out the memory cell or as a reference line which can be disposed on the base and/or on the substrate surface.
At points at which the MOS transistor is to be formed (the corresponding cells are referred to below, as in the quoted patent documents, as “first memory cells”), a suitable etching mask (so-called programming mask) is used to etch a hole into the first insulation material in the trench. The hole exposes the trench wall assigned to the first memory cell. At the other points, that is to say in the region of second memory cells which do not have a MOS transistor, and in the region between two memory cells which are adjacent in the direction of the trench, no hole is etched. In other words, the trench remains filled with the first insulation material. Then, a gate oxide is produced in the hole, and polysilicon, for example, is deposited and structured to form word lines, where the word lines run transversely with respect to the trenches. The word line here covers the gate oxide on the trench wall and thus forms the gate of the first memory cell. More details on the fabrication methods are described in the above-mentioned patent documents.
In the conventional fabrication methods, the following problems arise:
First, when the trench is filled with the insulating material, so-called shrinkage cavities may arise. These are porous weak points or holes which are produced approximately in the center of the trench as a growth joint if the deposited layer thickness is precisely half the width of the trench. As the trench fills up, the shrinkage cavities are buried. If the hole is subsequently etched using the programming mask to produce the transistor, the shrinkage cavity is opened at the sides, and, during the later deposition of the word-line material, the shrinkage cavity is filled with this conductive material, that is to say for example polysilicon to form the word lines. The buried polysilicon stringer cannot be removed during the structuring of the polysilicon into word lines. As a result, a short-circuit is produced between adjacent word lines, that is to say in particular between adjacent first memory cells.
Second, in order to ensure a reliable overlap of a word line and a programming hole in the event of alignment errors of the word line mask with respect to the programming mask, it is necessary in the conventional methods to select the width of the word lines to be greater than the width of the holes. As a rule of thumb, an alignment error of ⅓ F is to be calculated for a structure size F which has the minimum possible resolution, so that the width of the word lines must be {fraction (5/3)} F. Since the word-line spacing must be at least F, the word line grid spacing is increased to 2⅔ F.
SUMMARY OF THE INVENTION:
It is accordingly an object of the invention to provide a read-only memory cell array and method for fabricating it which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a read-only memory cell array, including: a semiconductor substrate; a cell matrix formed in the semiconductor substrate, the cell matrix has a plurality of strip-shaped trenches running essentially parallel with each other, the trenches have trench walls, the cell matrix includes first memory cells each having MOS transistors disposed vertically with respect to the semiconductor substrate, and second memory cells without any vertical MOS transistors, the first and second memory cells are disposed on predetermined sections of the trench walls; a gate dielectric and a gate electrode covering the trench walls in a region of the first memory cells, the MOS transistor disposed on the trench walls; a first insulation material covering the trench walls in a region of the second memory cells; a second insulation material and the gate dielectric disposed in the trenches between one of the first memory cells and one of another adjacent one of the first memory cells and one of the second memory cells adjacent in a direction of the trenches; and word lines running transversely with respect to the trenches and connected to the gate electrode respectively lying under the word lines.
In accordance with an added feature of the invention, the first insulation material includes TEOS, and the second insulation material includes one of TEOS and BPSG.
In accordance with another feature of the invention, the word lines have a width and the width is equal to a spacing between the word lines.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a read-only memory cell array has a cell matrix formed in a semiconductor substrate, the cell matrix includes first memory cells with vertical MOS transistors protruding upward from the semiconductor substrate along trenches, and second memory cells without any vertical MOS transistors, in combination with a mask for programming the read-only memory cell, including: a mask body covering areas of the second memory cells in the cell matrix, and leaving open areas between two adjacent first memory cells in a direction of the trenches.
With the foregoing and other objects in view there is further provided, in accordance with the invention, in a method for fabricating a read-only memory cell array having a cell matrix disposed in a semiconductor substrate, the cell matrix having first memory cells with MOS transistors and second memory cells without any MOS transistors, the improvement which includes: producing a plurality of strip-shaped trenches running essentially parallel to each other in the semiconductor substrate and forming the trenches with trench walls; forming MOS transistors essentially vertical with respect to the semiconductor substrate at predetermined points on the trench walls; filling the trenches with a first insulation material; removing the first insulation material in the cell matrix from the trenches at all points with the aid of a programming mask covering areas designated for second memory cells; depositing a gate dielectric and a conductive layer in the exposed trench walls for completing the MOS transistors; structuring the conductive layer to form strip-shaped word lines which run transvers
Kohlhase Armin
Trueby Alexander
Zimmermann Ulrich
Greenberg Laurence A.
Infineon - Technologies AG
Lee Eddie
Lerner Herbert L.
Stemer Werner H.
LandOfFree
Read-only memory cell array and method for fabricating it does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Read-only memory cell array and method for fabricating it, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read-only memory cell array and method for fabricating it will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2438891