Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-06-08
2000-05-16
Guay, John
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257391, 257411, H01L 27112
Patent
active
060641010
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor-based read-only memory cell arrangement which can be produced with both a small number of production steps and a high yield and which exhibits increased storage density.
2. Description of the Prior Art
Memories to which data are written permanently are required for many electronic systems. Such memories are referred to, inter alia, as read-only memories.
Plastic disks coated with aluminum are in wide-spread use as read-only memories for very large volumes of data. These plastic disks have two different kinds of point-like depressions in coating which are respectively assigned to the logic values zero and one. The information is stored digitally in the arrangement of these depressions. Such disks are referred to as compact disks and are widely used for the digital storage of music.
In order to read the data which are stored on a compact disk, the disk is rotated mechanically using a reading apparatus. The point-like depressions are scanned by means of a laser diode and a photocell. Typical scanning rates in this case are 2.times.40 kHz. 5 Gbits of information can be stored on one compact disk.
The reading apparatus has moving parts which are subjected to mechanical wear, require a comparatively large volume and allow only slow data access. The reading apparatus is furthermore sensitive to vibrations and can thus be used only to a limited extent in mobile systems. Semiconductor-based read-only memories are known for the storage of smaller volumes of data. These memories are often formed as a planar integrated silicon circuit in which MOS transistors are used. The MOS transistors are respectively selected via the gate electrode connected to the word line. The input of the MOS transistor is connected to a reference line while the output is connected to a bit line. An assessment is carried out during the reading operation to determine whether or not a current is flowing through the transistor. The stored information is assigned accordingly. In technical terms, the storage of the information is usually effected by the MOS transistors having different threshold voltages as a result of different implantation in the channel region.
These semiconductor-based memories allow random access to stored information. The electrical power required to read the information is distinctly less than in a reading apparatus having a mechanical drive. Since a mechanical drive is not required to read the information, the mechanical wear and the sensitivity to vibrations are obviated. Semiconductor-based read-only memories can therefore be used for mobile systems as well.
In order to increase the storage density in planar silicon memories, it has been proposed to arrange the MOS transistors in rows. In each row, the MOS transistors are connected in series. The MOS transistors are read out by row-by-row driving in the sense of a NAND or NOR architecture. This requires only two terminals per row wherein the MOS transistors arranged in the row are connected in series between the terminals. Source/drain regions, connected to one another, of neighboring MOS transistors can then be formed as a coherent doped region. This enables the area requirement per memory cell to be reduced to a theoretical value of 4F.sup.2 (F-smallest structure size that can be produced using the respective technology). Such a memory cell arrangement is disclosed, for example, in H. Kawagoe and N. Tsuji, IEEE J. Solid-State Circ., vol. SC-11, P. 360 (1976).
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor-based read-only memory cell arrangement in which an increased storage density is achieved and which can be produced with both a small number of production steps and a high yield. The present invention is further directed to a method for producing such a memory cell arrangement.
The read-only memory cell arrangement of the present invention includes a multiplicity of individual memory cells in a semiconductor substrate which is prefe
REFERENCES:
patent: 5300804 (1994-04-01), Arai
patent: 5306941 (1994-04-01), Yoshida
patent: 5453637 (1995-09-01), Chune et al.
patent: 5747856 (1998-05-01), Chen et al.
patent: 5751040 (1998-05-01), Chen et al.
Hofmann Franz
Krautschneider Wolfgang
Lau Frank
Guay John
Siemens Aktiengesellschaft
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